Uploaded July 2026 | Updated September 2026, 2 weeks ago
This video explores the powerful new analysis utilities in Innovator3D IC Integrator designed to help you manage complex SoC floor plans. Learn how to use the latest commands to report net line lengths and visualize net crossings, allowing you to identify congestion and optimize your design early in the process.
Whether you're working with massive HBM based designs or high-density SoC/chiplet designs, these tools provide the data you need to ensure signal integrity and efficient routing.
🛠️ Key Features Demonstrated:
1. Automated Length Reporting: Use report_net_line_length to get an instant breakdown of total lengths for signals, power, and ground nets.
2. Granular Control: Learn how to specify display units (like nanometers) and filter your reports to show only the specific data you need.
3. Targeted Analysis: See how to report the length of a single specific net by using the -name flag—perfect for checking critical timing paths.
4. Crossing Visualization: The new report_crossings command doesn't just give you a list; it places green icons directly on your floor plan to show exactly where lines overlap.
5. Categorized Summaries: View a detailed breakdown of crossings by type, including Signal-to-Signal, Signal-to-Power, and Power-to-Power.
💡 Why this matters:
In high-pin-count designs like HBM and SoC integration, net line crossings are a primary indicator of routing congestion. By visualizing these crossings and reporting net lengths before full routing, you can make informed floor planning decisions that reduce design iterations and improve final performance.
▶️ Connect with us:
» LinkedIn: https://sie.ag/4dQVGF
» Blog: https://sie.ag/6vcAei
» IC Packaging Community Discussion Board: https://sie.ag/3vZ7Ma
» X: https://sie.ag/3RZPw5
#Semiconductor #ElectricalEngineering #Innovator3DIC #3DICDesign
This video explores the powerful new analysis utilities in Innovator3D IC Integrator designed to help you manage complex SoC floor plans. Learn how to use the latest commands to report net line lengths and visualize net crossings, allowing you to identify congestion and optimize your design early in the process.
Whether you're working with massive HBM based designs or high-density SoC/chiplet designs, these tools provide the data you need to ensure signal integrity and efficient routing.
🛠️ Key Features Demonstrated:
1. Automated Length Reporting: Use report_net_line_length to get an instant breakdown of total lengths for signals, power, and ground nets.
2. Granular Control: Learn how to specify display units (like nanometers) and filter your reports to show only the specific data you need.
3. Targeted Analysis: See how to report the length of a single specific net by using the -name flag—perfect for checking critical timing paths.
4. Crossing Visualization: The new report_crossings command doesn't just give you a list; it places green icons directly on your floor plan to show exactly where lines overlap.
5. Categorized Summaries: View a detailed breakdown of crossings by type, including Signal-to-Signal, Signal-to-Power, and Power-to-Power.
💡 Why this matters:
In high-pin-count designs like HBM and SoC integration, net line crossings are a primary indicator of routing congestion. By visualizing these crossings and reporting net lengths before full routing, you can make informed floor planning decisions that reduce design iterations and improve final performance.
▶️ Connect with us:
» LinkedIn: https://sie.ag/4dQVGF
» Blog: https://sie.ag/6vcAei
» IC Packaging Community Discussion Board: https://sie.ag/3vZ7Ma
» X: https://sie.ag/3RZPw5
#Semiconductor #ElectricalEngineering #Innovator3DIC #3DICDesign
