Uploaded June 2026 | Updated September 2026, 2 weeks ago
As semiconductor designs grow in size and complexity, silicon and system debug has become harder across test, bench, and full-system environments. In this video, we explore the trends driving that complexity, including heterogeneous design content, advanced packaging, packetized test networks, high-speed I/O such as PCIe, and larger software loads.
You’ll learn how teams can improve debug visibility with automated failure mapping, scan dump techniques, and functional monitors such as Tessent Embedded Analytics. The discussion also covers how these methods support performance analysis, in-system test, and continuous in-field health monitoring as part of a broader system lifecycle management approach.
▶️Topics covered:
- Silicon and system debug challenges in complex SoCs
- Test access architecture and Streaming Scan Network
- Scan dump for higher-resolution debug visibility
- Functional monitors for software behavior and performance analysis
- In-system and in-field monitoring with Tessent technologies
🔗 Learn more about Tessent here: https://sie.ag/3hjQyw
▶️ Connect with us:
» LinkedIn: https://sie.ag/3yE88g
» EDA blogs: https://sie.ag/4Q2bWo
» IC Design Community Discussion Board: https://sie.ag/JW2MB
» X: https://sie.ag/2ukvfA
#EDA #Semiconductor #ElectronicsEngineering #DFT #SemiconductorTest
As semiconductor designs grow in size and complexity, silicon and system debug has become harder across test, bench, and full-system environments. In this video, we explore the trends driving that complexity, including heterogeneous design content, advanced packaging, packetized test networks, high-speed I/O such as PCIe, and larger software loads.
You’ll learn how teams can improve debug visibility with automated failure mapping, scan dump techniques, and functional monitors such as Tessent Embedded Analytics. The discussion also covers how these methods support performance analysis, in-system test, and continuous in-field health monitoring as part of a broader system lifecycle management approach.
▶️Topics covered:
- Silicon and system debug challenges in complex SoCs
- Test access architecture and Streaming Scan Network
- Scan dump for higher-resolution debug visibility
- Functional monitors for software behavior and performance analysis
- In-system and in-field monitoring with Tessent technologies
🔗 Learn more about Tessent here: https://sie.ag/3hjQyw
▶️ Connect with us:
» LinkedIn: https://sie.ag/3yE88g
» EDA blogs: https://sie.ag/4Q2bWo
» IC Design Community Discussion Board: https://sie.ag/JW2MB
» X: https://sie.ag/2ukvfA
#EDA #Semiconductor #ElectronicsEngineering #DFT #SemiconductorTest
