Uploaded December 2019 | Updated September 2026, 1 week ago
In this video I combine a number of smaller things I had been meaning to do that were not enough to justify a full video.
I explain the problem I had during the RAM video that I diagnosed and fixed between videos. Rather than being an address register sequencing problem as I dismissed this as it was actually a timing issue on the write enable line relative to the address changing. The fix was simple using a change to the circuit I had already discussed in the ram video.
I do a general tidy up replacing some patch wires with custom cut connections, I also add a decoupling cap to the miniature breadboard I'm using to introduce a delay to the bus controls clock.
I also fix the reset circuit, one aspect of this was disabled during the memory bridge work. I had previously commented that the delay added to the bus control clock line should fix the cause of that problem, I scope it out to confirm the fix and re-enable the feature.
In this video I combine a number of smaller things I had been meaning to do that were not enough to justify a full video.
I explain the problem I had during the RAM video that I diagnosed and fixed between videos. Rather than being an address register sequencing problem as I dismissed this as it was actually a timing issue on the write enable line relative to the address changing. The fix was simple using a change to the circuit I had already discussed in the ram video.
I do a general tidy up replacing some patch wires with custom cut connections, I also add a decoupling cap to the miniature breadboard I'm using to introduce a delay to the bus controls clock.
I also fix the reset circuit, one aspect of this was disabled during the memory bridge work. I had previously commented that the delay added to the bus control clock line should fix the cause of that problem, I scope it out to confirm the fix and re-enable the feature.
