Uploaded September 2025 | Updated September 2026, 3 weeks ago
Achieving robust timing closure is paramount in modern ASIC design. This talk delves into the critical role of physical synthesis and timing optimization within the OpenROAD flow, with a particular focus on its powerful Resizer module. This presentation will highlight the significant recent advancements and capabilities integrated into OpenROAD's Resizer. We will explore how these updates enhance its ability to perform sophisticated gate sizing, buffer insertion, and netlist restructuring, leading to improved power, performance, and area (PPA) metrics. Attendees will gain practical insights into effectively constraining their designs and harnessing the latest features of the OpenROAD Resizer to achieve superior timing closure results for their open-source hardware projects.
Prof. Guthaus also wants to meet up with others on Sunday to discuss timing closure challenges on your open-source projects.
Achieving robust timing closure is paramount in modern ASIC design. This talk delves into the critical role of physical synthesis and timing optimization within the OpenROAD flow, with a particular focus on its powerful Resizer module. This presentation will highlight the significant recent advancements and capabilities integrated into OpenROAD's Resizer. We will explore how these updates enhance its ability to perform sophisticated gate sizing, buffer insertion, and netlist restructuring, leading to improved power, performance, and area (PPA) metrics. Attendees will gain practical insights into effectively constraining their designs and harnessing the latest features of the OpenROAD Resizer to achieve superior timing closure results for their open-source hardware projects.
Prof. Guthaus also wants to meet up with others on Sunday to discuss timing closure challenges on your open-source projects.
