Uploaded May 2026 | Updated September 2026, 2 weeks ago
CHIPS Alliance hosts open source tools and IP blocks for ASIC development, and has a vision of aligning open source efforts towards building a tool suite for faster and more collaborative design and testing of silicon.
This talk will outline the activities and objectives of the recently restructured SV Tools project, concerned with SV development, testing and productivity with CHIPS-hosted tools like Verible, RISC-V DV or SV-tests and their integration with the broader open source tooling ecosystem, as well as new developments in the VeeR family of RISC-V cores, including the Guineveer SoC based on the Topwrap SoC generator.
CHIPS Alliance hosts open source tools and IP blocks for ASIC development, and has a vision of aligning open source efforts towards building a tool suite for faster and more collaborative design and testing of silicon.
This talk will outline the activities and objectives of the recently restructured SV Tools project, concerned with SV development, testing and productivity with CHIPS-hosted tools like Verible, RISC-V DV or SV-tests and their integration with the broader open source tooling ecosystem, as well as new developments in the VeeR family of RISC-V cores, including the Guineveer SoC based on the Topwrap SoC generator.
