Uploaded September 2025 | Updated September 2026, 2 weeks ago
Open source EDA has come a long way since I first "saw the light" while founding the parallel processor company Adapteva in 2008. In this talk I will present my journey as a user and contributor to open source EDA and point out some of the technology gaps that still remain. I will then explain how Zero ASIC leverages open source tools successfully in our day to day business model. Finally, I will present some of our existing projects (SiliconCompiler, Switchboard, Logik, Lambdalib, LambdaPDK, UMI) and disclose a brand new open source project.
Open source EDA has come a long way since I first "saw the light" while founding the parallel processor company Adapteva in 2008. In this talk I will present my journey as a user and contributor to open source EDA and point out some of the technology gaps that still remain. I will then explain how Zero ASIC leverages open source tools successfully in our day to day business model. Finally, I will present some of our existing projects (SiliconCompiler, Switchboard, Logik, Lambdalib, LambdaPDK, UMI) and disclose a brand new open source project.









, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor. Wildcat: Educational RISC-V Microprocessors (Martin Schoeberl)](https://i.ytimg.com/vi/nmtyEEVvkHw/mqdefault.jpg)
