Uploaded September 2025 | Updated September 2026, 2 weeks ago
A FABulous FPGA utilizing the Panamax padframe designed using open source EDA tools and the open source sky130 PDK.
Panamax FPGA features 64 I/Os, 1280 LCs (LUT4+FF), 8 MAC (8-bit * 8-bit + 20-bit), 16 register files (1w2r, 32x4) and 8 BRAM (dual-ported 1r1rw, 256x32). In addition, the FPGA fabric integrates some analog IP: 2 x 12-bit split-CDAC SAR ADC and 2 x 8-bit R-DAC.
Panamax FPGA was submitted for tapeout in May 2025.
A FABulous FPGA utilizing the Panamax padframe designed using open source EDA tools and the open source sky130 PDK.
Panamax FPGA features 64 I/Os, 1280 LCs (LUT4+FF), 8 MAC (8-bit * 8-bit + 20-bit), 16 register files (1w2r, 32x4) and 8 BRAM (dual-ported 1r1rw, 256x32). In addition, the FPGA fabric integrates some analog IP: 2 x 12-bit split-CDAC SAR ADC and 2 x 8-bit R-DAC.
Panamax FPGA was submitted for tapeout in May 2025.




, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor. Wildcat: Educational RISC-V Microprocessors (Martin Schoeberl)](https://i.ytimg.com/vi/nmtyEEVvkHw/mqdefault.jpg)





