Uploaded May 2026 | Updated September 2026, 2 weeks ago
Building on our ORConf 2025 verification in Verilator (fossi-foundation.org/orconf/2025#advancing-design-verification-with-verilator) presentation, in this talk we'll dive into further progress Antmicro and others have made with regard to Verilator's verification capabilities. We will cover topics like improvements to UVM compatibility, developments in assertion support, an overhaul of force/release statements, and the next big step for Verilator: four-state logic. We will also touch on tools that helped us get here, such as sv-bugpoint or CHIPS Alliance's sv-tests.
Building on our ORConf 2025 verification in Verilator (fossi-foundation.org/orconf/2025#advancing-design-verification-with-verilator) presentation, in this talk we'll dive into further progress Antmicro and others have made with regard to Verilator's verification capabilities. We will cover topics like improvements to UVM compatibility, developments in assertion support, an overhaul of force/release statements, and the next big step for Verilator: four-state logic. We will also touch on tools that helped us get here, such as sv-bugpoint or CHIPS Alliance's sv-tests.
