Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulat... W. Han & A. Sutton @RISCVInternational
Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulat... W. Han & A. Sutton  @RISCVInternational
Uploaded November 2025 | Updated September 2026, 1 week ago
Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulation Techniques - Weihua Han & Aimee Sutton, Synopsys

Simulation throughput has long been the bottleneck in achieving verification closure. Complex RISC-V designs have exacerbated this problem, requiring long-running tests and complex stimulus to ensure that the design is bug free. This talk presents a case study using an industry-standard test generator adapted for use with hardware emulation. The case study uses the open-source XiangShan RISC-V core as the example design under test. The presentation will outline the techniques employed to achieve comprehensive testing and high verification throughput while presenting evidence of the effectiveness of this approach at finding bugs. After attending the talk attendees facing similar challenges should feel empowered to try this approach.
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Verifying a Complex RISC-V Processor Using Test Generation and Hardware Emulat... W. Han & A. Sutton

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