Uploaded August 2024 | Updated September 2026, 3 weeks ago
Alphawave Semi talks about how it uses Keysight Chiplet PHY Designer to validate its IP and chips for UCIe compliance.
Learn more about what's new in high-speed digital design and simulation:
keysight.com/find/whats-new-in-high-speed-digital
Apply for a free trial of Advanced Design System (ADS):
keysight.com/find/ads-evaluation
Alphawave Semi talks about how it uses Keysight Chiplet PHY Designer to validate its IP and chips for UCIe compliance.
Learn more about what's new in high-speed digital design and simulation:
keysight.com/find/whats-new-in-high-speed-digital
Apply for a free trial of Advanced Design System (ADS):
keysight.com/find/ads-evaluation
![[4] EP-Scan for Design Improvements](https://i.ytimg.com/vi/mE9Evxp78ZQ/mqdefault.jpg "[4] EP-Scan for Design Improvements
Accelerate design improvements by reusing existing analysis setup for faster re-validation on revised layouts.
By the end of this session, PCB designers can:
- Export previously created test plans with compliance setup
- Apply existing test plans to updated designs
- Re-run analysis without rebuilding configurations
EP-Scan 2026 Download Page:
https://www.keysight.com/find/ep-scan-downloads
Apply for a Free Trial:
https://edaapps.software.keysight.com
Watch full EP‑Scan playlist:
https://www.youtube.com/playlist?list=PLtq84kH8xZ9G1mJrSbCQkSDGoqqiq7F0s
Reference layouts used in this playlist:
Download from Keysight EDA: https://www.keysight.com/us/en/assets/9926-01485/miscellaneous/reference-layout-EP-Scan-Introduction.zip")
