Uploaded August 2024 | Updated September 2026, 3 weeks ago
Are you facing challenges in chiplet system analysis?
Discover how Keysight's Chiplet PHY Designer (W3650B) simplifies the complexity of chiplet system analysis by providing industry-first, standard-driven analysis. In this video, we dive into the unique features of Chiplet PHY Designer, the first and only tool in the market to prioritize support for UCIe standards, including Quarter Data Rate (QDR) Clock and advanced Voltage Transfer Function (VTF) analysis for loss and crosstalk.
Chiplet designs demand rigorous end-to-end validation, and Chiplet PHY Designer is here to streamline your workflow. From the transmitter to the interconnect and receiver, this tool offers comprehensive system analysis with guided setup dialogs, reducing your setup time significantly. Chiplet PHY Designer automates VTF calculations and enables simulation of your chiplet system’s behavior before production.
Whether you're working with IBIS-AMI models or post-layout S-parameter simulations, Chiplet PHY Designer has got you covered. You can easily predict system performance, optimize your design, and generate professional reports with just one click.
Analyze your Chiplet Designs for free and stay ahead of the competition!: keysight.com/find/mytrial.si.vi
Download the latest ADS:
keysight.com/find/eesof-ads-latest-downloads
Thank you for watching! Subscribe for more updates and tutorials.
#ChipletDesign #UCIe #QDR #VoltageTransferFunction #VTF #Crosstalk #IBISAMI #KeysightEDA #SystemAnalysis #ChipletSystem
Are you facing challenges in chiplet system analysis?
Discover how Keysight's Chiplet PHY Designer (W3650B) simplifies the complexity of chiplet system analysis by providing industry-first, standard-driven analysis. In this video, we dive into the unique features of Chiplet PHY Designer, the first and only tool in the market to prioritize support for UCIe standards, including Quarter Data Rate (QDR) Clock and advanced Voltage Transfer Function (VTF) analysis for loss and crosstalk.
Chiplet designs demand rigorous end-to-end validation, and Chiplet PHY Designer is here to streamline your workflow. From the transmitter to the interconnect and receiver, this tool offers comprehensive system analysis with guided setup dialogs, reducing your setup time significantly. Chiplet PHY Designer automates VTF calculations and enables simulation of your chiplet system’s behavior before production.
Whether you're working with IBIS-AMI models or post-layout S-parameter simulations, Chiplet PHY Designer has got you covered. You can easily predict system performance, optimize your design, and generate professional reports with just one click.
Analyze your Chiplet Designs for free and stay ahead of the competition!: keysight.com/find/mytrial.si.vi
Download the latest ADS:
keysight.com/find/eesof-ads-latest-downloads
Thank you for watching! Subscribe for more updates and tutorials.
#ChipletDesign #UCIe #QDR #VoltageTransferFunction #VTF #Crosstalk #IBISAMI #KeysightEDA #SystemAnalysis #ChipletSystem









![[6] EP-Scan for Fabrication-Aware Design Checks
Ensure design robustness by evaluating performance under fabrication variation, enabling validation against realistic manufacturing conditions.
By the end of this session, PCB designers can:
- Incorporate fabrication effects directly into substrate definitions
- Model etch back and conductor geometry variations
- Re-evaluate performance metrics with updated stack up conditions
- Validate design margins under realistic fabrication scenarios
EP-Scan 2026 Download Page:
https://www.keysight.com/find/ep-scan-downloads
Apply for a Free Trial:
https://edaapps.software.keysight.com
Watch full EP‑Scan playlist:
https://www.youtube.com/playlist?list=PLtq84kH8xZ9G1mJrSbCQkSDGoqqiq7F0s
Reference layouts used in this playlist:
Download from Keysight EDA: https://www.keysight.com/us/en/assets/9926-01485/miscellaneous/reference-layout-EP-Scan-Introduction.zip [6] EP-Scan for Fabrication-Aware Design Checks](https://i.ytimg.com/vi/nkpeIg_W72Y/mqdefault.jpg)
![[5] EP-Scan for Composite Designs
Enable end‑to‑end channel analysis by incorporating lumped RLC components directly into the signal path.
By the end of this session, PCB designers can:
- Create composite nets integrating RLC lumped models
- Define component placement and electrical values
- Evaluate end to end channel performance including discrete components
EP-Scan 2026 Download Page:
https://www.keysight.com/find/ep-scan-downloads
Apply for a Free Trial:
https://edaapps.software.keysight.com
Watch full EP‑Scan playlist:
https://www.youtube.com/playlist?list=PLtq84kH8xZ9G1mJrSbCQkSDGoqqiq7F0s
Reference layouts used in this playlist:
Download from Keysight EDA: https://www.keysight.com/us/en/assets/9926-01485/miscellaneous/reference-layout-EP-Scan-Introduction.zip [5] EP-Scan for Composite Designs](https://i.ytimg.com/vi/nxYpY974QSA/mqdefault.jpg)