Uploaded August 2025 | Updated September 2026, 3 weeks ago
ADS 2026 Release: Boost Signal Integrity, Accelerate High-Speed Digital Design
Discover the latest features in Keysight ADS 2026 that take your signal integrity (SI) and power integrity (PI) analysis to the next level. Whether you're working on PCIe Gen7, LPDDR6, HBM3, or Ethernet system design, this release brings smarter tools and faster workflows to help you design with confidence.
What You'll Learn in This Video:
How to use the new System Designer for Ethernet (W3653B)
Accelerate pathfinding with SIPro Cell Sweep and Pathfinding Mode for PCIe and USB
Improve model automation with enhanced name parsing and Touchstone file parsing
Leverage Python scripting with the new Memory Designer Python API
Run PAM-n simulations and build your own AMI models with PCIe Gen7 support
Improve compliance with updated S-parameter Toolkit and Memory Mask validation tools
Explore support for Mueller-Muller phase detector and other system-level modeling features
Key Benefits for High-Speed Design Teams:
Maximize throughput with a scalable, standard-driven workflow
Predict performance early using trusted, standards-compliant simulation models
Increase design compliance and meet specs confidently in less time
Designed for:
Signal integrity and power integrity engineers
High-speed digital and memory system designers
Anyone working with PCIe, LPDDR, HBM, SerDes, or chiplet-based architectures
Chapters:
00:00 Intro
00:30 Ethernet System Designer
01:20 SIPro & Pathfinding for PCIe/USB
03:10 Memory Designer Updates
04:30 PCIe Gen7 Simulation Features
06:00 PAM-n & AMI Model Builder
07:30 Summary & Call to Action
Subscribe to stay up to date on the latest EDA tools for high-speed digital design.
Comment if you want us to dive deeper into a specific use case.
Like this video if you found it helpful for your design process.
#SignalIntegrity #ADS2026 #KeysightADS #PCIeGen7 #LPDDR6 #HBM3 #MemoryDesign #HighSpeedDesign #SerDes #Chiplet #Pathfinding #SIPro #SystemDesigner #Sparameter #AMIModeling #EDAtools #PythonAPI
ADS 2026 Release: Boost Signal Integrity, Accelerate High-Speed Digital Design
Discover the latest features in Keysight ADS 2026 that take your signal integrity (SI) and power integrity (PI) analysis to the next level. Whether you're working on PCIe Gen7, LPDDR6, HBM3, or Ethernet system design, this release brings smarter tools and faster workflows to help you design with confidence.
What You'll Learn in This Video:
How to use the new System Designer for Ethernet (W3653B)
Accelerate pathfinding with SIPro Cell Sweep and Pathfinding Mode for PCIe and USB
Improve model automation with enhanced name parsing and Touchstone file parsing
Leverage Python scripting with the new Memory Designer Python API
Run PAM-n simulations and build your own AMI models with PCIe Gen7 support
Improve compliance with updated S-parameter Toolkit and Memory Mask validation tools
Explore support for Mueller-Muller phase detector and other system-level modeling features
Key Benefits for High-Speed Design Teams:
Maximize throughput with a scalable, standard-driven workflow
Predict performance early using trusted, standards-compliant simulation models
Increase design compliance and meet specs confidently in less time
Designed for:
Signal integrity and power integrity engineers
High-speed digital and memory system designers
Anyone working with PCIe, LPDDR, HBM, SerDes, or chiplet-based architectures
Chapters:
00:00 Intro
00:30 Ethernet System Designer
01:20 SIPro & Pathfinding for PCIe/USB
03:10 Memory Designer Updates
04:30 PCIe Gen7 Simulation Features
06:00 PAM-n & AMI Model Builder
07:30 Summary & Call to Action
Subscribe to stay up to date on the latest EDA tools for high-speed digital design.
Comment if you want us to dive deeper into a specific use case.
Like this video if you found it helpful for your design process.
#SignalIntegrity #ADS2026 #KeysightADS #PCIeGen7 #LPDDR6 #HBM3 #MemoryDesign #HighSpeedDesign #SerDes #Chiplet #Pathfinding #SIPro #SystemDesigner #Sparameter #AMIModeling #EDAtools #PythonAPI
![[6] EP-Scan for Fabrication-Aware Design Checks
Ensure design robustness by evaluating performance under fabrication variation, enabling validation against realistic manufacturing conditions.
By the end of this session, PCB designers can:
- Incorporate fabrication effects directly into substrate definitions
- Model etch back and conductor geometry variations
- Re-evaluate performance metrics with updated stack up conditions
- Validate design margins under realistic fabrication scenarios
EP-Scan 2026 Download Page:
https://www.keysight.com/find/ep-scan-downloads
Apply for a Free Trial:
https://edaapps.software.keysight.com
Watch full EP‑Scan playlist:
https://www.youtube.com/playlist?list=PLtq84kH8xZ9G1mJrSbCQkSDGoqqiq7F0s
Reference layouts used in this playlist:
Download from Keysight EDA: https://www.keysight.com/us/en/assets/9926-01485/miscellaneous/reference-layout-EP-Scan-Introduction.zip [6] EP-Scan for Fabrication-Aware Design Checks](https://i.ytimg.com/vi/nkpeIg_W72Y/mqdefault.jpg)
![[5] EP-Scan for Composite Designs
Enable end‑to‑end channel analysis by incorporating lumped RLC components directly into the signal path.
By the end of this session, PCB designers can:
- Create composite nets integrating RLC lumped models
- Define component placement and electrical values
- Evaluate end to end channel performance including discrete components
EP-Scan 2026 Download Page:
https://www.keysight.com/find/ep-scan-downloads
Apply for a Free Trial:
https://edaapps.software.keysight.com
Watch full EP‑Scan playlist:
https://www.youtube.com/playlist?list=PLtq84kH8xZ9G1mJrSbCQkSDGoqqiq7F0s
Reference layouts used in this playlist:
Download from Keysight EDA: https://www.keysight.com/us/en/assets/9926-01485/miscellaneous/reference-layout-EP-Scan-Introduction.zip [5] EP-Scan for Composite Designs](https://i.ytimg.com/vi/nxYpY974QSA/mqdefault.jpg)








