Uploaded November 2025 | Updated September 2026, 2 weeks ago
Chiplets have become a near-overnight success with today’s rapid-fire data center conversion to AI. But today’s integration of HBM DRAM with multiple SOC chiplets is only the very beginning of a larger trend in which multiple incompatible technologies will adopt heterogeneous integration to connect new memory technologies with advanced logic chips to provide both significant energy savings and vastly-improved performance at a reduced price point. In this presentation analysts Tom Coughlin and Jim Handy will explain how memory technologies like MRAM, ReRAM, FRAM, and even PCM will eventually displace the DRAM HBM stacks used with xPUs, on-chip NOR flash and SRAM, and even NAND flash in many applications. They will explain how DRAM’s refresh mechanism and NAND and NOR flash’s energy-hogging writes will give way to much cooler memories that will be easier to integrate within the processor’s package, how processor die sizes will dramatically shrink through the use of new memory technologies to replace on-chip NOR and SRAM, and how the UCIe interface will allow these memories to compete to bring down overall costs. They will also show how the approach will not only reduce the purchase price per teraflop, but also how the energy costs per teraflop will also improve.
See how four new technologies will drive important changes in processor architecture: Making larger processors using chiplets, Interconnecting commodity chiplets through the UCIe interface, New persistent memory chips that will reduce power and cost by replacing DRAM, SRAM & flash, and Heterogeneous integration, to team new processes with standard logic. Learn how processor architecture will adopt these four new technologies using new hardware and software configurations that were previously too costly or otherwise undesireable. Understand why these new technologies are being seriously pursued by leading processor makers, and how they will help your system exceed its price/performance and power goals.
Presented by Jim Handy, Objective Analysis and Tom Coughlin, Coughlin Associates
Learn More:
• SDC Website: snia.org/sniadeveloper
• SNIA Website: snia.org
• SNIA Educational Library: snia.org/library
• X: twitter.com/SNIA
• LinkedIn: linkedin.com/company/snia
Chiplets have become a near-overnight success with today’s rapid-fire data center conversion to AI. But today’s integration of HBM DRAM with multiple SOC chiplets is only the very beginning of a larger trend in which multiple incompatible technologies will adopt heterogeneous integration to connect new memory technologies with advanced logic chips to provide both significant energy savings and vastly-improved performance at a reduced price point. In this presentation analysts Tom Coughlin and Jim Handy will explain how memory technologies like MRAM, ReRAM, FRAM, and even PCM will eventually displace the DRAM HBM stacks used with xPUs, on-chip NOR flash and SRAM, and even NAND flash in many applications. They will explain how DRAM’s refresh mechanism and NAND and NOR flash’s energy-hogging writes will give way to much cooler memories that will be easier to integrate within the processor’s package, how processor die sizes will dramatically shrink through the use of new memory technologies to replace on-chip NOR and SRAM, and how the UCIe interface will allow these memories to compete to bring down overall costs. They will also show how the approach will not only reduce the purchase price per teraflop, but also how the energy costs per teraflop will also improve.
See how four new technologies will drive important changes in processor architecture: Making larger processors using chiplets, Interconnecting commodity chiplets through the UCIe interface, New persistent memory chips that will reduce power and cost by replacing DRAM, SRAM & flash, and Heterogeneous integration, to team new processes with standard logic. Learn how processor architecture will adopt these four new technologies using new hardware and software configurations that were previously too costly or otherwise undesireable. Understand why these new technologies are being seriously pursued by leading processor makers, and how they will help your system exceed its price/performance and power goals.
Presented by Jim Handy, Objective Analysis and Tom Coughlin, Coughlin Associates
Learn More:
• SDC Website: snia.org/sniadeveloper
• SNIA Website: snia.org
• SNIA Educational Library: snia.org/library
• X: twitter.com/SNIA
• LinkedIn: linkedin.com/company/snia
