Uploaded July 2026 | Updated September 2026, 1 week ago
SPEAKER:
Daniel Thompson, RISCstar Solutions
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in Bologna, Italy.
WORKSHOP DESCRIPTION:
Join Daniel Thompson from RISCstar Solutions for a hands-on workshop exploring the powerful RISC-V Vector (RVV) extensions. You’ll learn the core concepts and design principles behind RVV and we will also compare them to the SIMD approaches of other architectures.
SIMD programming can dramatically accelerate performance across a wide range of compute-intensive tasks, from machine learning and signal processing to cryptography and beyond. The session will then dive into practical techniques for converting optimized C code from other instruction set architectures (ISAs) into RVV-based implementations. We’ll highlight key differences between fixed vector-length architectures on other ISA platforms, and RVV’s more flexible vector-length agnostic (VLA) approach.
Don’t miss this chance to sharpen your skills, push performance limits, and get hands-on with the future of vector computing.
RESOURCES:
drive.google.com/drive/u/2/folders/1txe6YXQyklWyn26YUaC5SqNQwuHrFHpj
SPEAKER:
Daniel Thompson, RISCstar Solutions
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in Bologna, Italy.
WORKSHOP DESCRIPTION:
Join Daniel Thompson from RISCstar Solutions for a hands-on workshop exploring the powerful RISC-V Vector (RVV) extensions. You’ll learn the core concepts and design principles behind RVV and we will also compare them to the SIMD approaches of other architectures.
SIMD programming can dramatically accelerate performance across a wide range of compute-intensive tasks, from machine learning and signal processing to cryptography and beyond. The session will then dive into practical techniques for converting optimized C code from other instruction set architectures (ISAs) into RVV-based implementations. We’ll highlight key differences between fixed vector-length architectures on other ISA platforms, and RVV’s more flexible vector-length agnostic (VLA) approach.
Don’t miss this chance to sharpen your skills, push performance limits, and get hands-on with the future of vector computing.
RESOURCES:
drive.google.com/drive/u/2/folders/1txe6YXQyklWyn26YUaC5SqNQwuHrFHpj
