AI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at Scale - Z. Paz & M. Evans @RISCVInternational
AI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at Scale - Z. Paz & M. Evans  @RISCVInternational
Uploaded November 2025 | Updated September 2026, 1 week ago
AI-Ready RISC-V Using On-Chip Monitoring for Performance and Reliability at Scale - Ziv Paz, proteanTecs & Marc Evans, Andes Technology

As complex SoCs are being developed to address growing demands in cloud and edge applications, RISC-V is becoming more popular, especially for AI applications. Increasing workloads, power consumption, silicon aging, and silent data corruption are making predictive monitoring essential for clustered training runs and high-compute, low-latency inference. This session, co-hosted by proteanTecs and Andes Technology, introduces a novel approach to mission-mode, in-situ monitoring that delivers real-time insights into timing margins, degradation, workload stress, and aging. Attendees will learn how integrating proteanTecs’ deep data IP into Andes’ AX45MPV vector processor enables predictive analytics for failure prevention, dynamic power optimization, and enhanced RISC-V system visibility, supporting the growing needs of inference, training, and scientific computing in high-performance environments.
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AI-Ready RISC-V Using On-Chip Monitoring for Performance & Reliability at Scale - Z. Paz & M. Evans

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