Uploaded July 2026 | Updated September 2026, 1 week ago
SPEAKER: Jeremy Bennett - Embecosm
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in Bologna, Italy.
WORKSHOP DESCRIPTION:
How to: Bringing up ExecuTorch on a RISC-V Microcontroller - In this workshop, the presenters will take you through the steps required to bring up standard ExecuTorch (PyTorch for embedded systems) for a new bare metal RISC-V microcontroller. It is based on the presenters' experience in bringing up commercially robust ExecuTorch implementations for RISC-V cores. The material here will form part of a forthcoming Embecosm application note on bringing up AI platforms on bare metal microcontrollers.
In the first part we will address the steps needed to create a new ahead-of-time processor for the chip, showing what is needed to delegate operations for the custom features of a RISC-V processor, how to plan for the memory hierarchy, and how to delegate for quantization. The examples will look at how to delegate for RISC-V custom ISA extensions.
In the second part, we will show how to modify the ExecuTorch runtime for a new RISC-V processor. We will address how to provide custom implementations of operations for the RISC-V processor. The examples will include use of the PULP SIMD ISA extension to provide a custom implementation of an 8-bit quantized operator.
We will conclude by looking ahead to areas beyond the scope of this workshop, including the use of DMA and double buffering, bare-metal multithreading and how to support customer accelerators such as GEMM units. We will touch on how the general approach is applicable to other AI systems, such as TensorFlow/LiteRT.
All the course materials are open source and will be available in advance via GitHub. The target processor is a Verilator model of the OpenHW Group CV32E40Pv2 core. The intention is that participants follow along with the steps, creating their own custom implementation.
RESOURCES: drive.google.com/drive/folders/1DuqMpI0qg2NzkOsJBV_b_mZEBYge44U7
SPEAKER: Jeremy Bennett - Embecosm
This session was a part of the Software track at the RISC-V Developer Workshops held at RISC-V Summit Europe 2026 in Bologna, Italy.
WORKSHOP DESCRIPTION:
How to: Bringing up ExecuTorch on a RISC-V Microcontroller - In this workshop, the presenters will take you through the steps required to bring up standard ExecuTorch (PyTorch for embedded systems) for a new bare metal RISC-V microcontroller. It is based on the presenters' experience in bringing up commercially robust ExecuTorch implementations for RISC-V cores. The material here will form part of a forthcoming Embecosm application note on bringing up AI platforms on bare metal microcontrollers.
In the first part we will address the steps needed to create a new ahead-of-time processor for the chip, showing what is needed to delegate operations for the custom features of a RISC-V processor, how to plan for the memory hierarchy, and how to delegate for quantization. The examples will look at how to delegate for RISC-V custom ISA extensions.
In the second part, we will show how to modify the ExecuTorch runtime for a new RISC-V processor. We will address how to provide custom implementations of operations for the RISC-V processor. The examples will include use of the PULP SIMD ISA extension to provide a custom implementation of an 8-bit quantized operator.
We will conclude by looking ahead to areas beyond the scope of this workshop, including the use of DMA and double buffering, bare-metal multithreading and how to support customer accelerators such as GEMM units. We will touch on how the general approach is applicable to other AI systems, such as TensorFlow/LiteRT.
All the course materials are open source and will be available in advance via GitHub. The target processor is a Verilator model of the OpenHW Group CV32E40Pv2 core. The intention is that participants follow along with the steps, creating their own custom implementation.
RESOURCES: drive.google.com/drive/folders/1DuqMpI0qg2NzkOsJBV_b_mZEBYge44U7
