Uploaded November 2025 | Updated September 2026, 2 weeks ago
How NOT To Program an Out-of-order Vector Processor - Dongjie Xie & Chip Kerchner, Tenstorrent
High-performance, out-of-order RISC-V Vector (RVV) processors are now emerging, yet most hand-written and compiler-generated vector code is still designed for simpler, in-order CPUs. These older practices—such as explicit register renaming, manual dependency avoidance, and conservative approaches to instructions like vrgather and vcompress—often hinder performance when used on modern, superscalar vector hardware, which now manages dependencies and register allocation in hardware. In particular, conventional strip mining loops and segmented memory handling may unnecessarily bottleneck throughput. This talk provides updated programming guidelines for advanced RVA23-compliant designs, showing how to eliminate outdated workarounds and write more portable, efficient code. Concrete examples will illustrate how to best express parallelism, leverage high-throughput segmented loads/stores, and avoid pitfalls that limit the speedups these new RVV processors enable.
How NOT To Program an Out-of-order Vector Processor - Dongjie Xie & Chip Kerchner, Tenstorrent
High-performance, out-of-order RISC-V Vector (RVV) processors are now emerging, yet most hand-written and compiler-generated vector code is still designed for simpler, in-order CPUs. These older practices—such as explicit register renaming, manual dependency avoidance, and conservative approaches to instructions like vrgather and vcompress—often hinder performance when used on modern, superscalar vector hardware, which now manages dependencies and register allocation in hardware. In particular, conventional strip mining loops and segmented memory handling may unnecessarily bottleneck throughput. This talk provides updated programming guidelines for advanced RVA23-compliant designs, showing how to eliminate outdated workarounds and write more portable, efficient code. Concrete examples will illustrate how to best express parallelism, leverage high-throughput segmented loads/stores, and avoid pitfalls that limit the speedups these new RVV processors enable.
