Uploaded November 2025 | Updated September 2026, 2 weeks ago
Automated Certification and Benchmarking for RISC-V Architectures - Enrique Pallares, Quintauris
As the complexity of RISC-V designs grows, especially in safety-critical domains like automotive, the lack of standardized benchmarking and validation methodologies poses a serious challenge to integration, performance assessment, and certifiability. This session presents a technical exploration into the design of a reproducible and scalable benchmarking workflow for RISC-V SoCs, targeting both functional and non-functional metrics such as latency, jitter, IPC, and determinism.
We will discuss the integration of simulation-based and hardware-based (FPGA) environments, as well as how to define benchmarking suites that can be applied across diverse platforms. Special focus will be given to traceability, metric alignment with safety standards (e.g., ISO 26262), and managing architectural diversity within a unified evaluation pipeline. Challenges such as toolchain variability, IP heterogeneity, and maintaining reproducibility across environments will be addressed, along with the strategies adopted to mitigate them.
Rather than introducing a product, the session will walk through the real-world technical decisions behind building a robust RISC-V benchmarking strategy that supports future certification and interoperability efforts.
Automated Certification and Benchmarking for RISC-V Architectures - Enrique Pallares, Quintauris
As the complexity of RISC-V designs grows, especially in safety-critical domains like automotive, the lack of standardized benchmarking and validation methodologies poses a serious challenge to integration, performance assessment, and certifiability. This session presents a technical exploration into the design of a reproducible and scalable benchmarking workflow for RISC-V SoCs, targeting both functional and non-functional metrics such as latency, jitter, IPC, and determinism.
We will discuss the integration of simulation-based and hardware-based (FPGA) environments, as well as how to define benchmarking suites that can be applied across diverse platforms. Special focus will be given to traceability, metric alignment with safety standards (e.g., ISO 26262), and managing architectural diversity within a unified evaluation pipeline. Challenges such as toolchain variability, IP heterogeneity, and maintaining reproducibility across environments will be addressed, along with the strategies adopted to mitigate them.
Rather than introducing a product, the session will walk through the real-world technical decisions behind building a robust RISC-V benchmarking strategy that supports future certification and interoperability efforts.
