RISC-V: Enabler of an Open Source Hardware Era - Zeeshan Rafique, Usman Institute of Technology @RISCVInternational
RISC-V: Enabler of an Open Source Hardware Era - Zeeshan Rafique, Usman Institute of Technology @RISCVInternational
Updated September 2026, 2 weeks ago
RISC-V: Enabler of an Open Source Hardware Era - Zeeshan Rafique, Usman Institute of TechnologyPorting SIMD to RISC-V Vectors | Corrected AudioPolarFire SOC and Ecosystem NeedE4 | Demo Theatre | RISC-V Summit Europe 2026Nuclei | Demo Theatre | RISC-V Summit Europe 2026SiFive Event Trace: The First Zero-Overhead Performance Tool for RISC-V Processors - Carsten GosvigScaling Success You need big and small workloads for optimum balanceDeterministic Compute for Automotive SafetyAccelerating RISC-V Innovation with openMPACT Tools from Google | Jeremiassen, Mullings-Black, WangChipIN Centre: Accelerating India’s Journey in RISC-V - Venkata Reddy K & Aneesh Raveendran, C-DAC“One Student One Chip” - Learn to Create Your Own RISC-V Processor From ScratchHeterogeneity and Standardization
RISC-V International |

RISC-V: Enabler of an Open Source Hardware Era - Zeeshan Rafique, Usman Institute of Technology

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