Uploaded November 2025 | Updated September 2026, 2 weeks ago
ChipIN Centre: Accelerating India’s Journey in RISC-V - Venkata Reddy K & Aneesh Raveendran, C-DAC Bangalore
ChipIN Centre at C-DAC Bangalore is a national facility established to accelerate and catalyze indigenous chip design. It provides centralized access to industry-grade EDA tools, Multi-Project Wafer (MPW) prototyping, FPGA-based prototyping platforms, compute resources through the Param Utkarsh Supercomputing Facility, as well as enablement support for IC packaging and post-silicon validation—along with several other resources—serving academia, researchers, startups, and MSMEs across India.
RISC-V–based designs are gaining momentum under national initiatives such as Chips to Startup (C2S) Programme and Design Linked Incentive (DLI) Scheme, alongside a wide range of digital and mixed-signal design efforts. Through C2S, more than 285 academic institutions, and under DLI, over 70 startups are leveraging ChipIN infrastructure to develop IPs, RISC-V–based SoCs, and commercial products. Some of these efforts also build upon indigenous processor cores such as VEGA (C-DAC) and SHAKTI (IIT Madras).
The talk will also share insights from the Digital India RISC-V (DIR-V) Grand Challenge, launched under C2S Programme, which is incubating 30 startups and enabling the development of innovative RISC-V solutions. By lowering entry barriers and providing access to advanced tools, prototyping, training, and mentorship, ChipIN Centre is playing a pivotal role in advancing SoC development and strengthening India’s path toward semiconductor self-reliance.
ChipIN Centre: Accelerating India’s Journey in RISC-V - Venkata Reddy K & Aneesh Raveendran, C-DAC Bangalore
ChipIN Centre at C-DAC Bangalore is a national facility established to accelerate and catalyze indigenous chip design. It provides centralized access to industry-grade EDA tools, Multi-Project Wafer (MPW) prototyping, FPGA-based prototyping platforms, compute resources through the Param Utkarsh Supercomputing Facility, as well as enablement support for IC packaging and post-silicon validation—along with several other resources—serving academia, researchers, startups, and MSMEs across India.
RISC-V–based designs are gaining momentum under national initiatives such as Chips to Startup (C2S) Programme and Design Linked Incentive (DLI) Scheme, alongside a wide range of digital and mixed-signal design efforts. Through C2S, more than 285 academic institutions, and under DLI, over 70 startups are leveraging ChipIN infrastructure to develop IPs, RISC-V–based SoCs, and commercial products. Some of these efforts also build upon indigenous processor cores such as VEGA (C-DAC) and SHAKTI (IIT Madras).
The talk will also share insights from the Digital India RISC-V (DIR-V) Grand Challenge, launched under C2S Programme, which is incubating 30 startups and enabling the development of innovative RISC-V solutions. By lowering entry barriers and providing access to advanced tools, prototyping, training, and mentorship, ChipIN Centre is playing a pivotal role in advancing SoC development and strengthening India’s path toward semiconductor self-reliance.
