SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification | Yinan Xu @RISCVInternational
SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification | Yinan Xu @RISCVInternational
Uploaded July 2026 | Updated September 2026, 2 weeks ago
At RISC-V Summit Europe 2026

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Yinan Xu

Institute of Computing Technology, Chinese Academy of Sciences

Beijing Institute of Open Source Chip
SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification | Yinan Xuredbeard at RISC-V Summit NA 2025The Path to Industrial Deployment of Open-Source High-Performance RISC-V Processor | Yungang BaoPanel: Delivering the Future of Software Enablement for RISC-VDeveloping an Open AgenticSOC | Tanya DadashevaAccelera Digital In Memory Compute@brekerverificationsystems4973 at RISC-V Summit NA 2025MIPS | Demo Theatre | RISC-V Summit Europe 2026Matrix Extensions for RISC-VDelivering on the Promise | Dr. Philipp TomsichSemidynamics | embedded world 2026CEA | Demo Theatre | RISC-V Summit Europe 2026Andes | embedded world 2026
RISC-V International |

SVM: A Synthesizable Approach to Efficient RISC-V CPU Verification | Yinan Xu

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