Uploaded July 2026 | Updated September 2026, 2 weeks ago
In this demonstration, learn how to estimate net line resistance using stackup editor values and user-defined configuration files.
The video walks through how to add a new signal layer in the stackup editor, define key layer parameters such as thickness, color, resistivity, and material type, and then use those values to calculate total net line resistance. You’ll also see how to generate resistance results from the console and save them to a report log for further analysis.
The demo also covers an alternate workflow using a user input configuration file in CSV format. This allows users to define parameters such as interposer type, die trace width, design layer, resistivity, layer thickness, and routing factors, then run net line resistance estimation through the command line.
This workflow helps designers quickly evaluate routing resistance across nets and supports more informed analysis during the IC package or interposer design
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#Semiconductor #ElectricalEngineering #Innovator3DIC #3DICDesign
In this demonstration, learn how to estimate net line resistance using stackup editor values and user-defined configuration files.
The video walks through how to add a new signal layer in the stackup editor, define key layer parameters such as thickness, color, resistivity, and material type, and then use those values to calculate total net line resistance. You’ll also see how to generate resistance results from the console and save them to a report log for further analysis.
The demo also covers an alternate workflow using a user input configuration file in CSV format. This allows users to define parameters such as interposer type, die trace width, design layer, resistivity, layer thickness, and routing factors, then run net line resistance estimation through the command line.
This workflow helps designers quickly evaluate routing resistance across nets and supports more informed analysis during the IC package or interposer design
▶️ Connect with us:
» LinkedIn: https://sie.ag/3Yur6L
» Blog: https://sie.ag/56LFHb
» IC Packaging Community Discussion Board: https://sie.ag/XFgfX
» X: https://sie.ag/6SLVaw
#Semiconductor #ElectricalEngineering #Innovator3DIC #3DICDesign










