URCL Fizzbuzz on the MPU6 CPU @ModPunchtree
URCL Fizzbuzz on the MPU6 CPU  @ModPunchtree
Uploaded February 2021 | Updated September 2026, 2 weeks ago
This is running a Fizzbuzz program which was written in URCL which was then compiled into mpu6 assembly.
For Fizzbuzz the URCL version ran roughly 57% slower than the equivalent program written natively in mpu6 assembly.

MPU6.0 Specs:
5 tick clock speed (0.5 seconds)
4 stage pipe (with dual instruction fetching to speed up conditional instructions)
8 bit word length
uses a custom version of VLIW arch
10 general purpose registers
32 bytes of RAM
128 word instruction ROM (split into 2 lots of 64 for dual fetching)
8 bit hardware multiplier
32 bit BCD converter
16x8 Pixel Display
10x5, 8 Segment Char Display (using the MPU-64 character set)

Join the URCL (Universal Redstone Computer Language) discord:
discord.gg/jWRr2vx
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URCL Fizzbuzz on the MPU6 CPU

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