Ultra Low Power RISC-V Core Retention with Warm Restart Extension | Anne Merlande @RISCVInternational
Ultra Low Power RISC-V Core Retention with Warm Restart Extension | Anne Merlande @RISCVInternational
Uploaded July 2026 | Updated September 2026, 2 weeks ago
At RISC-V Summit Europe 2026

--
Anne Merlande, STMicroelectronics
Ultra Low Power RISC-V Core Retention with Warm Restart Extension | Anne MerlandeFabien from @Scaleway-cloud at RISC-V Summit NA 2025RHEL on SiFive for the win@akeana_riscv at RISC-V Summit NA 2025Community - Jefro - at RISC-V Summit NA 2025RISC-V Everywhere: From IoT to HPC - John Leidel, Tactical Computing LabsRVA23 Profile Support in the Linux Kernel | Guodong Xu and Charlie JenkinsRISC-V Technical Session | From RISC-V Cores to Neuromorphic ArraysSemidynamics at embedded world 2026Practical Implications of SPMP-based Virtualization | Manuel RodríguezBOSC | Demo Theatre | RISC-V Summit Europe 2026Demo: Akeana: Highest Performance, Customized Cores, Multi-core/Multi-thread Clusters- Graham Wilson
RISC-V International |

Ultra Low Power RISC-V Core Retention with Warm Restart Extension | Anne Merlande

SHARE TO X SHARE TO REDDIT SHARE TO FACEBOOK WALLPAPER