RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays @RISCVInternational
RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays  @RISCVInternational
Uploaded April 2026 | Updated September 2026, 1 week ago
This talk presents a research journey from energy-efficient RISC-V processor design toward neuromorphic computing architectures for embedded AI. It highlights how principles from digital hardware design, processor architecture, and hardware/software co-design can be applied to build scalable, efficient neuromorphic systems.

Presenter: Amir Yousefzadeh, University of Twente, Assistant Professor

Dr. Amir Yousefzadeh is an Assistant Professor at the University of Twente, the Netherlands, where he works on embedded AI, computer architecture, and neuromorphic systems. His research focuses on the design of energy-efficient hardware and algorithms for intelligent edge devices, with emphasis on neuromorphic computing, RISC-V-based architectures, and hardware/software co-design for AI workloads.
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RISC-V Technical Session | From RISC-V Cores to Neuromorphic Arrays

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