SerDes Basics 3: Signals, timing and sampling @SiemensSoftware
SerDes Basics 3: Signals, timing and sampling  @SiemensSoftware
Uploaded July 2026 | Updated September 2026, 2 weeks ago
In this video, we explain how digital data is transmitted as analog signals and why timing is critical for proper data recovery. Concepts such as waveform behavior, transitions, and sampling are introduced to build intuition for how receivers interpret incoming data.

This series covers the fundamentals of high-speed SerDes systems, including signal behavior, channel impairments, equalization, and performance metrics. It is intended for engineers, students, and anyone interested in signal integrity and high-speed digital design.
00:00 – Introduction to class and recap previous video

00:45 – Signals Are Not Ideal
01:36 – Why Timing Matters
02:33 – Clocking in the Transmitter
03:41 – Clock Data Recovery
04:15 – CDR Operations
05:12 – Sampling Decisions
06:28 – Timing Window
07:38 – Differential Signaling
08:16 – Why We Use Differential Signaling
09:12 – Putting It All Together
09:59 – Key Takeaways

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SerDes Basics 3: Signals, timing and sampling

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