Uploaded July 2026 | Updated September 2026, 2 weeks ago
In this video, we break down the architecture of a SerDes link and walk through how data moves from the transmitter to the receiver. We introduce the key building blocks of a high-speed communication system and explain the role each plays, providing a complete system-level view of signal flow.
This series covers the fundamentals of high-speed SerDes systems, including signal behavior, channel impairments, equalization, and performance metrics. It is intended for engineers, students, and anyone interested in signal integrity and high-speed digital design.
00:00 – Introduction to class and recap previous video
01:05 – SerDes Link Overview
01:34 – Serializer
03:01 – Transmitter Driver
03:49 – Transmitter Architecture
04:24 – The Physical Channel
05:01 – Channel Behavior in the Frequency Domain
06:03 – Impact on the Signal (ISI & Distortion)
06:55 – The Receiver
07:24 – Front-End Conditioning and Equalization
07:58 – Timing Recovery
08:53 – Receiver Architecture
09:55 – End-to-End System
10:53 – Key Takeaways
▶️ Connect with us:
» LinkedIn: https://sie.ag/679Tu1
» Blog: https://sie.ag/5GX1JT
» HyperLynx Community Discussion Board: https://sie.ag/62tvnt
#PCBDesign #SignalIntegrity #PowerIntegrity #ElectricalEngineering #Engineering #SerDes
In this video, we break down the architecture of a SerDes link and walk through how data moves from the transmitter to the receiver. We introduce the key building blocks of a high-speed communication system and explain the role each plays, providing a complete system-level view of signal flow.
This series covers the fundamentals of high-speed SerDes systems, including signal behavior, channel impairments, equalization, and performance metrics. It is intended for engineers, students, and anyone interested in signal integrity and high-speed digital design.
00:00 – Introduction to class and recap previous video
01:05 – SerDes Link Overview
01:34 – Serializer
03:01 – Transmitter Driver
03:49 – Transmitter Architecture
04:24 – The Physical Channel
05:01 – Channel Behavior in the Frequency Domain
06:03 – Impact on the Signal (ISI & Distortion)
06:55 – The Receiver
07:24 – Front-End Conditioning and Equalization
07:58 – Timing Recovery
08:53 – Receiver Architecture
09:55 – End-to-End System
10:53 – Key Takeaways
▶️ Connect with us:
» LinkedIn: https://sie.ag/679Tu1
» Blog: https://sie.ag/5GX1JT
» HyperLynx Community Discussion Board: https://sie.ag/62tvnt
#PCBDesign #SignalIntegrity #PowerIntegrity #ElectricalEngineering #Engineering #SerDes
