RISC-V Technical Session | Programming RISC V Accelerators via Fortran @RISCVInternational
RISC-V Technical Session | Programming RISC V Accelerators via Fortran  @RISCVInternational
Uploaded December 2025 | Updated September 2026, 2 weeks ago
A range of RISC-V based accelerators are available and coming to market, and there is strong potential for these to be used for High Performance Computing (HPC) workloads as they can deliver performance, energy and cost benefits. However, such accelerators tend to provide bespoke programming models and APIs that require codes to be rewritten. In scientific computing, where many of the simulation code are highly complex and written in Fortran, this is not realistic. In this talk I will describe an approach we have been developing that, based on MLIR, enables driving such architectures via Fortran and common HPC programming models, delivering performance whilst avoiding code redevelopment.
RISC-V Technical Session | Programming RISC V Accelerators via FortranEpic Semi | Demo Theatre | RISC-V Summit Europe 2026Berberis: Dynamic Binary Translation from RISC-V to X86_64 on... - Lev Rumyantsev & Jeremiah GriffinMandatory Server Features   FDOSecurity Extensions RoadmapState of the Union | Krste AsanovicLightning Round | | embedded world 2026Andes Technology at embedded world 2026A Proof-of-Concept RISC-V with 128-bit Extension | Frédéric PétrotOpen Hours October 12, 2022Andrea Gallo Meets BOSCs Dr. Yinan Xu | RISC-V Summit Europe 26Circuit Sutra at RISC-V Summit NA 2025
RISC-V International |

RISC-V Technical Session | Programming RISC V Accelerators via Fortran

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