A Proof-of-Concept RISC-V with 128-bit Extension | Frédéric Pétrot @RISCVInternational
A Proof-of-Concept RISC-V with 128-bit Extension | Frédéric Pétrot @RISCVInternational
Uploaded July 2026 | Updated September 2026, 2 weeks ago
At RISC-V Summit Europe 2026

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Frédéric Pétrot, Univ. Grenoble Alpes, CNRS, Inria, Grenoble INP*, TIMA, F-38000 Grenoble, France
A Proof-of-Concept RISC-V with 128-bit Extension | Frédéric PétrotOpen Hours October 12, 2022Andrea Gallo Meets BOSCs Dr. Yinan Xu | RISC-V Summit Europe 26Circuit Sutra at RISC-V Summit NA 2025SiFive Your Trusted Partner in IP | embedded world 2026Next-Generation Edge AI with RISC-V Vector Cores for Vision Applications - Florian ZarubaTransforming MCUs in an AI-Defined Era | Edward WilfordPorting Potholes Boring but Critical BugsSpacemiT at RISC-V Summit NA 2025RISC-V Opportunities in Brazil - J. E.Bertuzzo, Eldorado InstitutePerformance Leap to Skylake ClassRISC-V Summit Europe 2024
RISC-V International |

A Proof-of-Concept RISC-V with 128-bit Extension | Frédéric Pétrot

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