Uploaded November 2025 | Updated September 2026, 2 weeks ago
Networking-Native RISC-V Processor for Datacenter - Mark Throndson, MIPS
Datacenters rely on high-bandwidth and low-latency interconnects to provide scalability of compute and storage resources. Within the networking infrastructure, the ability to route and parse packets efficiently is critical, and removing any overhead associated with this function immediately impacts efficiency in terms of latency and power. With the inherent flexibility and standard constructs of the RISC-V architecture, there are several optimizations that can be achieved within a standard RISC-V solution that tailor the implementation to networking.
MIPS’ multi-threaded I8500 CPU brings this focus by implementing a big-endian-native CPU and compute cluster, allowing for packet header and payload data to be natively processed in network byte order, removing the overhead of performing any byte swizzling within hardware gates or in software instructions. Additionally, the CPUs have several features well suited for managing packet flow through a larger system, such as a short pipeline, availability of memory mapped SRAM in addition to cache hierarchy, and deterministic response times to interrupts and system events. Each CPU has 4-way simultaneous multithreading (SMT) and supports a scalable with multi-core solution with multiple cores in a local cluster and coherency for multi-cluster designs.
This paper will explore the I8500 implementation of these features that target RISC-V to the heart of datacenter networking infrastructure, and how the scalable design allows for a wide range of networking applications.
Audience will learn:
* Key considerations for processors within networking infrastructure of datacenter applications
* Use of RISC-V constructs and architectural support for harts, big endian mode and how they contribute to and complement a multi-core/multi-cluster capable CPU subsystem for networking centric functions.
* cost-benefit tradeoff
Networking-Native RISC-V Processor for Datacenter - Mark Throndson, MIPS
Datacenters rely on high-bandwidth and low-latency interconnects to provide scalability of compute and storage resources. Within the networking infrastructure, the ability to route and parse packets efficiently is critical, and removing any overhead associated with this function immediately impacts efficiency in terms of latency and power. With the inherent flexibility and standard constructs of the RISC-V architecture, there are several optimizations that can be achieved within a standard RISC-V solution that tailor the implementation to networking.
MIPS’ multi-threaded I8500 CPU brings this focus by implementing a big-endian-native CPU and compute cluster, allowing for packet header and payload data to be natively processed in network byte order, removing the overhead of performing any byte swizzling within hardware gates or in software instructions. Additionally, the CPUs have several features well suited for managing packet flow through a larger system, such as a short pipeline, availability of memory mapped SRAM in addition to cache hierarchy, and deterministic response times to interrupts and system events. Each CPU has 4-way simultaneous multithreading (SMT) and supports a scalable with multi-core solution with multiple cores in a local cluster and coherency for multi-cluster designs.
This paper will explore the I8500 implementation of these features that target RISC-V to the heart of datacenter networking infrastructure, and how the scalable design allows for a wide range of networking applications.
Audience will learn:
* Key considerations for processors within networking infrastructure of datacenter applications
* Use of RISC-V constructs and architectural support for harts, big endian mode and how they contribute to and complement a multi-core/multi-cluster capable CPU subsystem for networking centric functions.
* cost-benefit tradeoff
