Featured Work: Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform @RISCVInternational
Featured Work: Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform  @RISCVInternational
Uploaded August 2026 | Updated September 2026, 2 weeks ago
This project reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V cloud server and accelerator prototypes capable of running fully-featured Linux-based software stacks. Building on processor IP from the EPI and EUPILOT projects, RISER targets Europe's open strategic autonomy in cloud infrastructure. We present the RISER Microserver Platform, an FPGA-assisted prototype that integrates the EPAC1.5 RISC-V vector-processor test-chip in a standalone computing node with its own boot firmware, NVMe storage, and 100 Gbps Ethernet connectivity, and discuss the integration challenges encountered during bring-up and initial validation of use-cases.
Featured Work: Integration Challenges in RISC-V System Prototyping: The RISER Microserver PlatformRISC-V Server Platform 1.0 One Spec to Boot Them All | Radim KrčmářEvaluating Tenstorrent RISC-V Accelerators For High Performance Scientific Computing | BoellaForecast Exceeding Expectations due to China DataAn Open-Source CVA6S+ High-Performance, Cache-Coherent Cluster for 64b Automotive MPUs | R. TedeschiTenstorrent: Extending the RISC-V Open Source Ecosystem - Darshak Koshiya, TenstorrentRISC Vs Foundational Financial SuccessCommunity - Carl Perry - at RISC-V Summit NA 2025@AndesTechnology  at RISC-V Summit NA 2025RISC-V CPU IP Own Your Silicon Future | tenstorrent | | embedded world 2026@tenstorrentinc  at RISC-V Summit NA 2025A User-Friendly and AI-Ready Desktop for RISC-V: Bianbu LXQt | Xiaogang Fan
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Featured Work: Integration Challenges in RISC-V System Prototyping: The RISER Microserver Platform

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