Uploaded September 2019 | Updated September 2026, 1 week ago
The Memory Bridge connects the memory data bus and the main bus and makes memory operate a bit like a register to the rest of the cpu. The terminology can get a bit confusing, a "bus assert" operation is a memory read and a "load" operation is a write.
There is no ram at the moment so we can't fully implement write, but we can get the data onto the memory data bus and test everything else.
I do discover a small problem with a modification I made to the "bus request" line building the reset circuit, I'll save that for another day. It wasn't essential.
The Memory Bridge connects the memory data bus and the main bus and makes memory operate a bit like a register to the rest of the cpu. The terminology can get a bit confusing, a "bus assert" operation is a memory read and a "load" operation is a write.
There is no ram at the moment so we can't fully implement write, but we can get the data onto the memory data bus and test everything else.
I do discover a small problem with a modification I made to the "bus request" line building the reset circuit, I'll save that for another day. It wasn't essential.
