Uploaded December 2019 | Updated September 2026, 3 weeks ago
Tutorial 1, Hot Chips 31 (2019), Sunday, August 18, 2019.
Organizer: Christos Kozyrakis, Stanford
The Nitro Project — Next Generation AWS Infrastructure
Anthony Liguori, Amazon Web Services (AWS)
This tutorial focuses on the evolution of hypervisors, their interactions with servers and I/O chips. Specifically, it will cover the architecture of the modern Nitro hypervisor and Nitro chips for the AWS infrastructure, including the Nitro networking, storage and HPC chips. It will also discuss how can developers use this infrastructure.
Acceleration at Microsoft
Derek Chiou, Eric Chung, and Susan Carrie, Microsoft
This talk describes Microsoft’s balanced acceleration efforts that include FPGAs and ASICs. FPGAs provide programmability with hardware performance, while ASICs provide density, power, and cost advantages for fixed functions. Two examples, specifically, the Project Brainwave effort targeting DNN inference on FPGAs and the Corsica Project Zipline compression ASIC, will be described. Microsoft is moving towards open accelerator eco-systems as demonstrated by the release of the Project Zipline compression standard with RTL code.
TPU V3 in Google Cloud: Architecture and Infrastructure
Clifford Chao & Brennan Saeta, Google
This tutorial covers the TPU v3 chip architecture and the large-scale TPU-based systems available on Google Cloud. It also covers the TPU software design choices that allows scaling from a single chip to a large-scale system with no customer code changes.
Tutorial 1, Hot Chips 31 (2019), Sunday, August 18, 2019.
Organizer: Christos Kozyrakis, Stanford
The Nitro Project — Next Generation AWS Infrastructure
Anthony Liguori, Amazon Web Services (AWS)
This tutorial focuses on the evolution of hypervisors, their interactions with servers and I/O chips. Specifically, it will cover the architecture of the modern Nitro hypervisor and Nitro chips for the AWS infrastructure, including the Nitro networking, storage and HPC chips. It will also discuss how can developers use this infrastructure.
Acceleration at Microsoft
Derek Chiou, Eric Chung, and Susan Carrie, Microsoft
This talk describes Microsoft’s balanced acceleration efforts that include FPGAs and ASICs. FPGAs provide programmability with hardware performance, while ASICs provide density, power, and cost advantages for fixed functions. Two examples, specifically, the Project Brainwave effort targeting DNN inference on FPGAs and the Corsica Project Zipline compression ASIC, will be described. Microsoft is moving towards open accelerator eco-systems as demonstrated by the release of the Project Zipline compression standard with RTL code.
TPU V3 in Google Cloud: Architecture and Infrastructure
Clifford Chao & Brennan Saeta, Google
This tutorial covers the TPU v3 chip architecture and the large-scale TPU-based systems available on Google Cloud. It also covers the TPU software design choices that allows scaling from a single chip to a large-scale system with no customer code changes.
