Uploaded July 2026 | Updated September 2026, 16 hours ago
This was Open Research Institute's FPGA Meetup on June 9, 2026, where Michelle provided updates on the development of satellite receiver systems using FPGA and processor implementations. Michelle reported progress on implementing a channelizer for 64 channels on a ZCU102 development board and optimizing demodulation and decoding between FPGA fabric and A53 quad-core processor, with 24 channels successfully fitted in the processor version. Aaron was working on implementing the entire system including Viterbi decoder on FPGA, though facing resource constraints. The team discussed challenges with resource allocation between FPGA and processor, with Michelle proposing to split the implementation at the frame sync word decoder level to accommodate all 64 channels in the processor. Paul provided test bench support using a Libre SDR connected to the ZCU102 for interoperability testing between different implementations. Rick shared updates from DSCS including radio astronomy work, EVE project preparations, and recent successful testing of their dish at 8.5 GHz for Deep Space Network operations, receiving signals from Chinese satellites and Mars rovers. The conversation ended with discussions about EME (Earth-Moon-Earth) signal testing and the need for documentation on using SIGMF files with SDRs for EME operations.
Thank you to everyone helping us do ambitious work!
This was Open Research Institute's FPGA Meetup on June 9, 2026, where Michelle provided updates on the development of satellite receiver systems using FPGA and processor implementations. Michelle reported progress on implementing a channelizer for 64 channels on a ZCU102 development board and optimizing demodulation and decoding between FPGA fabric and A53 quad-core processor, with 24 channels successfully fitted in the processor version. Aaron was working on implementing the entire system including Viterbi decoder on FPGA, though facing resource constraints. The team discussed challenges with resource allocation between FPGA and processor, with Michelle proposing to split the implementation at the frame sync word decoder level to accommodate all 64 channels in the processor. Paul provided test bench support using a Libre SDR connected to the ZCU102 for interoperability testing between different implementations. Rick shared updates from DSCS including radio astronomy work, EVE project preparations, and recent successful testing of their dish at 8.5 GHz for Deep Space Network operations, receiving signals from Chinese satellites and Mars rovers. The conversation ended with discussions about EME (Earth-Moon-Earth) signal testing and the need for documentation on using SIGMF files with SDRs for EME operations.
Thank you to everyone helping us do ambitious work!
