Uploaded July 2025 | Updated September 2026, 2 weeks ago

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2025 AsiaLLVM Developers' Meeting

llvm.org/devmtg/2025-06

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Title: Data-Tiling in IREE: Achieving High Performance Through Compiler Design

Speakers: Han-Chung Wang

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Slides: llvm.org/devmtg/2025-06/slides/technical-talk/wang-data-tilling.pdf

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This talk explores how IREE, a retargetable MLIR-based compiler for tensor programs, achieves high performance through data-tiling. By rearranging input data into target-specific layouts and utilizing tensor encodings, IREE bridges the gap between host and device. These encodings enable efficient data handling and unlock optimizations like folding, fusion, and propagation, which reduce the cost of relayouting operations. Learn how IREE integrates data-tiling to optimize performance in a compiler context.

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