Worlds first lunar exploration rover using FPGA-based RISC-V processor | Tetsuo Yoshimitsu @RISCVInternational
Worlds first lunar exploration rover using FPGA-based RISC-V processor | Tetsuo Yoshimitsu  @RISCVInternational
Uploaded July 2026 | Updated September 2026, 2 weeks ago
At RISC-V Summit Europe 2026

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Tetsuo YOSHIMITSU (ISAS/JAXA)

Tomoyuki HIROSE (Digital Spice Co. Ltd)

Yasuharu KUNII (Chuo University)
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RISC-V International |

World's first lunar exploration rover using FPGA-based RISC-V processor | Tetsuo Yoshimitsu

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