Mike Fikes | SHENZHEN I/O problem 1 in hardware @MikeFikes | Uploaded January 2018 | Updated October 2024, 1 hour ago.
A solution to problem 1 in SHENZHEN I/O (zachtronics.com/shenzhen-io) using logic chips. Here is how it works:
On the left is a 555 timer chip which is used to generate the CLK signal.
To produce the active (ACTV) signal (which is a square wave with a period of 12 clock cycles), the CLK signal is first inverted (via a 74HCT04, with is the 4th chip from the left), and then fed into a 74LS90 (the 2nd chip from the left). The 74LS90 is set up to divide-by-6 (see p. 231 of _TTL Cookbook_) with the output coming out of pin 6. This output is low for 4 cycles and high for 2 cycles. To convert this to the desired square wave, it is fed into a JK flip-flop (a 74LS76, 3rd chip from left) set up to toggle with every negative edge, thus producing the ACTV square wave which is displayed via the red LED, and the 2nd trace on the oscilloscope.
The problem solution is the network (NETW) signal, displayed by the bottom trace on the oscilloscope. It needs to be low for 4 cycles, high for 2, followed by low and high for 1 cycle each. To produce it, first a binary counter is used (a 74HCT161, the farthest chip on the right). If you let the three lowest-order bits of this counter be t0 through t2, the solution is given by t2 ∧ (¬t1 ∨ t0). To express this using only ANDs and NOTs, it is re-expressed as t2 ∧ ¬(t1 ∧ ¬t0). This is calculated by using a QUAD-input AND chip (74HCT08, 2nd from right), and the existing HEX inverter to the left of it, with the result being displayed with the blue led.
A solution to problem 1 in SHENZHEN I/O (zachtronics.com/shenzhen-io) using logic chips. Here is how it works:
On the left is a 555 timer chip which is used to generate the CLK signal.
To produce the active (ACTV) signal (which is a square wave with a period of 12 clock cycles), the CLK signal is first inverted (via a 74HCT04, with is the 4th chip from the left), and then fed into a 74LS90 (the 2nd chip from the left). The 74LS90 is set up to divide-by-6 (see p. 231 of _TTL Cookbook_) with the output coming out of pin 6. This output is low for 4 cycles and high for 2 cycles. To convert this to the desired square wave, it is fed into a JK flip-flop (a 74LS76, 3rd chip from left) set up to toggle with every negative edge, thus producing the ACTV square wave which is displayed via the red LED, and the 2nd trace on the oscilloscope.
The problem solution is the network (NETW) signal, displayed by the bottom trace on the oscilloscope. It needs to be low for 4 cycles, high for 2, followed by low and high for 1 cycle each. To produce it, first a binary counter is used (a 74HCT161, the farthest chip on the right). If you let the three lowest-order bits of this counter be t0 through t2, the solution is given by t2 ∧ (¬t1 ∨ t0). To express this using only ANDs and NOTs, it is re-expressed as t2 ∧ ¬(t1 ∧ ¬t0). This is calculated by using a QUAD-input AND chip (74HCT08, 2nd from right), and the existing HEX inverter to the left of it, with the result being displayed with the blue led.
