Reduce Digital Feedback in Data Conversion Systems - Linear Technology @LinearTechnology
Reduce Digital Feedback in Data Conversion Systems - Linear Technology  @LinearTechnology
Uploaded March 2009 | Updated September 2026, 3 weeks ago
with Clarence Mayott, Applications Engineer - High Speed Data Converter Products
video.linear.com/22?utm_source=highspeedADC&utm_medium=video&utm_campaign=youtube

Linear Technology's newest high-speed ADC family achieves 1/3rd the power consumption of existing solutions without compromising AC performance. Operating from a low 1.8V supply, the 14-bit, 125Msps LTC2261 (linear.com/product/LTC2261-14) dissipates 125mW while maintaining 73.4dB SNR and 85dBc SFDR. Digital outputs can be configured as DDR CMOS, DDR LVDS or standard CMOS for minimizing FPGA pin count. An optional alternate bit polarity mode is provided to reduce the effects of digital feedback.
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Reduce Digital Feedback in Data Conversion Systems - Linear Technology

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