Uploaded October 2025 | Updated September 2026, 2 weeks ago
Our series of deep dive sessions from Intel Technology Tour 2025 continues with Sr. Principal Engineer and SoC Architect Arik Gihon, who unpacks Panther Lake’s scalable architecture and its key components. This overview of the processor explains how it’s all stitched together, from internal fabrics, caching, and memory through to the Foveros technology that physically connects the tiles. Learn about the family of pin-compatible die package combinations designed to meet the needs of different devices, the new IP shared across the line, and the gains we’re seeing in both performance and efficiency.
Follow along for more information about Panther Lake: youtube.com/playlist?list=PL8t1FdN2Tj3a8dkQruuF8ZytUaxE4EwQQ
See Panther Lake in action at Computex: youtu.be/GuQQ9jXCQL4?si=lJjutRvlfznIq2Hm
Chapters:
00:00 – Introduction
01:30 – Architected for scalability
02:18 – Scalable fabric
04:03 – Tiles and construction
05:05 – Memory and platform flexibility
06:36 – Pin compatible family
07:31 – 8 core config
09:49 – 16 core config
11:12 – 16 core 12Xe config
12:42 – Comparing configurations
14:25 – Cougar Cove and Darkmont cores
16:41 – Xe3 GPU
17:28 – NPU5
18:35 – IPU 7.5
19:25 – Xe Media Engine
20:26 – Upgraded efficiency cluster
21:00 – Memory-side cache
21:48 – Thread Director & power management
24:00 – Performance and efficiency gains
26:11 – Platform summary
About Intel Technology:
Intel has always been at the forefront of developing exciting new technology for business and consumers including emerging technologies, data center servers, business transformation, memory and storage, security, and graphics. The Intel Technology YouTube channel is a place to learn tips and tricks, get the latest news, and watch product demos from both Intel and our many partners across multiple fields.
Connect with Intel Technology:
Visit Intel Technologies WEBSITE: intel.ly/IntelTechnologies
Our series of deep dive sessions from Intel Technology Tour 2025 continues with Sr. Principal Engineer and SoC Architect Arik Gihon, who unpacks Panther Lake’s scalable architecture and its key components. This overview of the processor explains how it’s all stitched together, from internal fabrics, caching, and memory through to the Foveros technology that physically connects the tiles. Learn about the family of pin-compatible die package combinations designed to meet the needs of different devices, the new IP shared across the line, and the gains we’re seeing in both performance and efficiency.
Follow along for more information about Panther Lake: youtube.com/playlist?list=PL8t1FdN2Tj3a8dkQruuF8ZytUaxE4EwQQ
See Panther Lake in action at Computex: youtu.be/GuQQ9jXCQL4?si=lJjutRvlfznIq2Hm
Chapters:
00:00 – Introduction
01:30 – Architected for scalability
02:18 – Scalable fabric
04:03 – Tiles and construction
05:05 – Memory and platform flexibility
06:36 – Pin compatible family
07:31 – 8 core config
09:49 – 16 core config
11:12 – 16 core 12Xe config
12:42 – Comparing configurations
14:25 – Cougar Cove and Darkmont cores
16:41 – Xe3 GPU
17:28 – NPU5
18:35 – IPU 7.5
19:25 – Xe Media Engine
20:26 – Upgraded efficiency cluster
21:00 – Memory-side cache
21:48 – Thread Director & power management
24:00 – Performance and efficiency gains
26:11 – Platform summary
About Intel Technology:
Intel has always been at the forefront of developing exciting new technology for business and consumers including emerging technologies, data center servers, business transformation, memory and storage, security, and graphics. The Intel Technology YouTube channel is a place to learn tips and tricks, get the latest news, and watch product demos from both Intel and our many partners across multiple fields.
Connect with Intel Technology:
Visit Intel Technologies WEBSITE: intel.ly/IntelTechnologies
