Uploaded December 2019 | Updated September 2026, 3 weeks ago

---

Session 6, Hot Chips 31 (2019), Tuesday, August 20, 2019.

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator Designed with a High-Productivity VLSI Methodology
Rangharajan Venkatesan, Nvidia

Xilinx Versal/AI Engine
Sagheer Ahmad & Sridhar Subramanian, Xilinx

Spring Hill — Intel’s Data Center Inference Chip
Ofri Wechsler, Michael Behar & Bharat Daga, Intel