Uploaded March 2026 | Updated September 2026, 57 minutes ago
FPGAs let you design custom silicon, but the tooling is stuck in the '90s. What if you could skip Verilog and describe hardware in Elixir instead?
Hardwire is an Elixir HDL that uses macros to compile a familiar DSL — if/else, case, module composition — straight into digital logic. No runtime tracing, no magic. Just compile-time metaprogramming all the way down to a bitstream you can flash onto real hardware.
We'll walk through the pipeline from Elixir source to running on an FPGA, the DSL design tradeoffs that make it feel like Elixir while still being synthesizable hardware, and what happens when you point Elixir's macro system at a problem it was never designed for.
FPGAs let you design custom silicon, but the tooling is stuck in the '90s. What if you could skip Verilog and describe hardware in Elixir instead?
Hardwire is an Elixir HDL that uses macros to compile a familiar DSL — if/else, case, module composition — straight into digital logic. No runtime tracing, no magic. Just compile-time metaprogramming all the way down to a bitstream you can flash onto real hardware.
We'll walk through the pipeline from Elixir source to running on an FPGA, the DSL design tradeoffs that make it feel like Elixir while still being synthesizable hardware, and what happens when you point Elixir's macro system at a problem it was never designed for.
