Gerry Builds a Custom Adapter to Help Decipher a 90s Era Altera MAX CPLD Erase Sequence  [#64] @BehindTheCode_wGerry
Gerry Builds a Custom Adapter to Help Decipher a 90s Era Altera MAX CPLD Erase Sequence  [#64]  @BehindTheCode_wGerry
Uploaded December 2025 | Updated September 2026, 2 weeks ago
In this video I build a DIY adapter for my Data I/O Labsite Universal programmer.

This Custom adapter is outfitted with IDC headers for interfacing a Logic Analyzer to the inserted device for running logical scans on the chips pins while it is in circuit during an Erase sequence.

Building this adapter is to assist in the DIY community with their attempts of building a very simple Eraser module to help Students and Hobby electronics members Erase 90's era Altera MAX 7000S devices that are in a state of JTAG Lockout. Building this adapter is the first step to gathering the logic data needed to decipher the Erase sequence for these CPLD devices.

Data I/O EPROM Group on Groups.io :
groups.io/g/DataioEPROM


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Gerry Builds a Custom Adapter to Help Decipher a 90's Era Altera MAX CPLD Erase Sequence [#64]

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