Exploring with my new Scope - Making an 8 Bit pipelined CPU - Part 58 @weirdboyjim
Exploring with my new Scope - Making an 8 Bit pipelined CPU - Part 58  @weirdboyjim
Uploaded November 2019 | Updated September 2026, 1 week ago
I've bought myself an oscilloscope, this video is my first exploration of the cpu build testing a few assumptions and learning about the analogue side of things in the build.

Spoilers:

I find the master clock rises comparatively slowly, the 555 timer isn't a high speed logic part so I clean that up by passing it thru a couple of spare invertors. I also take the led display of separately as it's obvious that the led is effecting the line (No doubt I'll need to pay attention to this elsewhere).

I discover the clock to the bus control isn't delayed as much as I thought, I add a nice big delay there (I'll drop this down once things are stable again, I just wanted to completely eliminate it being an issue).

I find there is a noticeable amount of noise between the ground in the register stack and ground in the pipeline. I resolve it with a direct ground link, this appears to have completely resolved the superflous counting issue.

Finally I identify a 1 cycle long burst of noise which seems to be associated with the indirect memory reads, I'll leave that for future troubleshooting.
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Exploring with my new Scope - Making an 8 Bit pipelined CPU - Part 58

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