Exceptional Trap Handling: RISC-V ep.10 @LowByteProductions
Exceptional Trap Handling: RISC-V ep.10  @LowByteProductions
Uploaded April 2022 | Updated September 2026, 2 weeks ago
In this episode of the RISC-V quest, we're implementing the mechanics of trap handling, taking one particularly easy to spot exception as the focus point: Load Address Misaligned.

The design involves building a new module, as well as a new super-state of the CPU, which controls when the processor is executing the pipeline, and when it is handling the mechanics of traps.

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Exceptional Trap Handling: RISC-V ep.10

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