1920x1080p @ 60FPS #ComputerEngineering #FixedPoint #TutorialBuilding a 5Hz 16bit Matrix Multiply Unit -feat NanoWildEngineering2022-10-01 | Wow its been a while since last playing MC and now we are working on revamping the matrix multiply unit for a different precision.
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2560x1080p @ 60FPS #ComputerEngineering #Minecraft #redstoneBuilding a 5Hz 16bit Matrix Multiply Unit -feat NanoWildEngineering2022-09-08 | Wow its been a while since last playing MC and now we are working on revamping the matrix multiply unit for a different precision.
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2560x1080p @ 60FPS #ComputerEngineering #Minecraft #redstoneBuilding a 5Hz 16bit Matrix Multiply Unit -feat NanoWildEngineering2022-08-26 | Wow its been a while since last playing MC and now we are working on revamping the matrix multiply unit for a different precision.
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2560x1080p @ 60FPS #ComputerEngineering #Minecraft #redstoneBobbyCore - The first fully functional RISC-V CPU in Logic World!WildEngineering2022-04-23 | Gnog3 had originally built a RISC-V core that was almost complete but lacked function calls. I asked if would like to work on a v2 with me, which we embarked on around January of 2022.
Bobbycore hardware is nearing completion, we are now working on writing libraries and example codes to show what is possible to be programmed on the strongest CPU in LW to date.
Specs: arch: Von Neumann RV32I speed: 12 tick clock, this includes instruction fetch and execute as it is single cycle von neumann. RAM: Previously 64KB, now 16MB, with support for virtual memory LANGS: C/C++ and support for the stdlib, Rust, RISC-V ASM IO: 11 tick Multiplier, 128 tick Divider, 6 tick line drawer, tick perfect character and integer printer, 107 key n-key rollover keyboard, array copy hardware, fill-screen/plot pixel, and a 256x256 24bit RGB 10fps display. Extra Goodies: Program counter display with integrated hardware breakpoint. Boot Loader 1 - TCP Programmer, Boot Loader 2 - ROM Programmer.
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1920x1080p @ 60FPS #ComputerEngineering #RISCV #CPULogic World Bresenhams Line Drawer: Tutorial #5WildEngineering2022-04-09 | God this took a long time to edit/render. Vegas kept messing up the end of the video so I rendered the first several clips and the last clip separate, then re-rendered as a whole video. That worked, except now there's 3 mins of black nothing at the end of the video for some reason so... Enjoy!
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1920x1080p @ 60FPS #ComputerEngineering #Bresenham #ASICLogic World Bresenhams Line Drawer: Tutorial #4WildEngineering2022-01-30 | In this installment we attach the up down counters made in part 3 to the build, then build the decrement logic loop for cmpt.
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1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #ASICLogic World Bresenhams Line Drawer: Tutorial #3, Up/Down Counter w/ BranchingWildEngineering2022-01-29 | In this episode we build the up/down counter with branching to enable us to move to the next part of the algorithm.
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1920x1080p @ 60FPS #LogicWorld #Linedrawer #TutorialLogic World Bresenhams Line Drawer: Tutorial #2WildEngineering2022-01-23 | Here is part 2 of the linedrawer tutorial series. In this installment, we wrap up the combinational input logic. Please leave any questions in the comments and I will try to answer them ASAP.
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1920x1080p @ 60FPS #LogicWorld #Linedrawer #TutorialLogic World Bresenhams Line Drawer: Tutorial #1WildEngineering2022-01-17 | So here we are, starting a series on making a Bresenham's line drawer. I hope you follow along and create a successful build at the end of the series. Please leave any questions in the comments and I will try to answer them ASAP. _________________________________________________________________________________________________ TIMESTAMPS: INTRO: 00:00 - 03:23 ALGORITHM OVERVIEW: 03:23 - 12:40 START OF BUILD: 12:40 - 37:54 _________________________________________________________________________________________________ If you enjoy my content: Please consider SUBSCRIBING http://goo.gl/OTW7ox Join the WildEngineering Discord Here: discord.gg/dnMhEsC Donate here if you want to help support mepaypal.me/thewildjarvi ERC20 wallet: 0xE7a1de73A7b70C2aCBf01E39029b18d709D66F1A
1920x1080p @ 60FPS #LogicWorld #Linedrawer #TutorialBuilding a Mandelbrot Renderer in Logic WorldWildEngineering2021-12-22 | I'm a little bored so I figured I'd do this today. Were going to have to make some dank vedic squarers to optimize this and make it different from other peoples implementations. go big or go home
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2560x1080p @ 60FPS #ComputerEngineering #LogicWorld #MandelbrotBresenhams Linedrawer in Logic WorldWildEngineering2021-12-19 | So I got back into logic world and made this the other day in about an hour after I made the display. If you want the world file available for DL lmk.
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1920x1080p @ 60FPS #ComputerEngineering #Bresenham #ASICIntelliRuby, a custom 32bit CPU: Update October 2021WildEngineering2021-10-15 | I have been working on intelliRUBY and have some progress to show off! let me know what you think in the comments below!
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1920x1080p @ 60FPS #ComputerEngineering #CPU #ArchitectureBuilding a 32bit MIPS/RISCV Style CPU in DigitalWildEngineering2021-09-13 | like cmon building a pipelined cpu in minecraft is starting to get hard so I want to take a break and work on a bigger architecture with a huge ass instruction width of 57 bits.
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2560x1080p @ 60FPS #ComputerEngineering #DigitalLogic #CPUBuilding a 32bit MIPS/RISCV Style CPU in DigitalWildEngineering2021-09-11 | like cmon building a pipelined cpu in minecraft is starting to get hard so I want to take a break and work on a bigger architecture with a huge ass instruction width of 54 bits.
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1920x1080p @ 60FPS #ComputerEngineering #Minecraft #CPUBuilding a 32bit MIPS/RISCV Style CPU in DigitalWildEngineering2021-09-08 | like cmon building a pipelined cpu in minecraft is starting to get hard so I want to take a break and work on a bigger architecture with a huge ass instruction width of 54 bits.
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1920x1080p @ 60FPS #ComputerEngineering #Minecraft #CPUBuilding a 2Hz CPU in MC part 3, the AssemblerWildEngineering2021-08-15 | I'm working on an assembler in python for the new architecture I am calling μRed.
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1920x1080p @ 60FPS #ComputerEngineering #Minecraft #CPUBuilding a 2Hz CPU in MCWildEngineering2021-07-28 | Okay im going to attempt to make a 2HZ cpu
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1920x1080p @ 60FPS #ComputerEngineering #Minecraft #CPUIs this the fastest solid state multiplier in MC? + GPU UPDATEWildEngineering2021-04-21 | Nano, Penscii and I have been working on a new multiplier design. As you can see from the intro montage, we went through several iterations. The first one in the montage is the original multiplier in the 2D GPU I made a video on a few months ago.
This is a major break through for solid state 5Hz builds. The multiplier is 1+8.7 fixed point, meaning 1 sign, 8 integers, and 7 fractional bits. It has a total delay of 46 RT.
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Music Jash's sound cloud: soundcloud.com/s5yirr1glkak the fat rat - unity 1920x1080p @ 60FPS #Minecraft #Multiplier #GPU32 bit RISCV CPU Design Live StreamWildEngineering2021-04-03 | I am working in digital to make a RISC-V CPU . We will still start with the R type instructions
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1920x1080p @ 60FPS #ComputerEngineering #RISCV #CPU32 bit RISCV CPU Design Live StreamWildEngineering2021-03-28 | I am working in digital to make a RISC-V CPU . We will still start with the R type instructions
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1920x1080p @ 60FPS #ComputerEngineering #RISCV #CPU32 bit RISCV CPU Design Live StreamWildEngineering2021-03-06 | I am working in digital to make a RISC-V CPU but first I need some byte addressable RAM.
1920x1080p @ 60FPS #ComputerEngineering #RISCV #CPUMandelbrot Fractal Circuit Tutorial: Part 5 RENDERING THE MANDELBROT SET!WildEngineering2021-02-19 | In today's video we will finish the Mandelbrot circuit and watch as it appears before our eyes at the end of the video.
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #tutorialMandelbrot Fractal Circuit Tutorial: Part 4 Updating Component Shapes in SVG formatWildEngineering2021-02-19 | In today's video we will update the shape of our components before we finish the mandelbrot renderer!
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #tutorialMandelbrot Fractal Circuit Tutorial: Part 3 Finishing the Iterator Circuit.WildEngineering2021-02-07 | In today's video we will make a new circuit called 'iterate' which will iterate the recursive function that defines mandelbrot. I hope you all enjoy.
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #tutorialMandelbrot Fractal Circuit Tutorial: Part 2 Creating the Iterator generation circuitWildEngineering2021-01-23 | In today's video we will make a new circuit called 'generate' which will generate a^2 -b^2 , a^2 + b^2, and 2ab from the inputs a and b.
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #tutorialMandelbrot Fractal Circuit Tutorial: Part 1 Mapping the X Y Plane to the Complex PlaneWildEngineering2021-01-14 | In today's video we use the circuit we made in part 0 to generate the complex values that will be fed into our Mandelbrot math unit.
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #TutorialMandelbrot Fractal Circuit Tutorial: Part 0 Generating a pattern on a screen.WildEngineering2021-01-10 | Hello Wildengineers, This is the beginning of a tutorial series on how to build a Mandelbrot renderer in hardware. To follow along make sure you have downloaded the simulator I am using called "Digital" found here: github.com/hneemann/Digital
In part 0 we generate the pixel addresses for a 1024x768 screen and we then test that circuit at the end of the video to make sure it is working correctly. Stay tuned for the next tutorial!
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #TutorialWorking on a 32bit fixed point mandelbrot rendererWildEngineering2020-12-21 | I am working in digital to make this mandelbrot renderer! ask any questions you might have in the chat. - jarvi
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #ASIC5Hz Divider Showcase by Nano and TheWildJarviWildEngineering2020-11-05 | Keeping with the trend of 2RT pipe-able logic(5Hz logic) this is an 8 bit divider that Nano spearheaded the design of and I helped implement.
The ROM inputs are: Dividend = [42, 42, 21, 144, 81] Divsor = [6, 7, 3, 12, 9]
And the result as follows: Quotient = [7, 6, 7, 12, 9]
We need this circuit for doing the 3D to 2D projection for our cube renderer. That's why it needed to be 5Hz.
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1920x1080p @ 60FPS #ComputerEngineering #Divider #PipelinedDigital Tutorial 0: Why not Logisim?WildEngineering2020-10-31 | Alongside the other content I am making in Minecraft, I will be uploading videos on logic made in Digital, the free digital logic simulator.
This video is an overview of the functionality of Digital and why Im using it over a legacy software like logisim or any fork of logisim. You can find the github here: github.com/hneemann/Digital
1920x1080p @ 60FPS #ComputerEngineering #DigitalLogic #TutorialWe built a legit GPU in Minecraft(5Hz)WildEngineering2020-10-15 | So this happens to be one of the coolest things I have ever had the opportunity to build in MC. Nano convinced me to help him build this, and well, its been complete for about 5 months now. We just wanted to hold off on showing it until we were committed to making a full on render engine in MC.
TLDR: we have a vector image stored in 2RT serial ROM that we can scale, rotate by any angle, and move around on the screen. :)
This is able to perform a 2x1 * 2x2 vector multiplication, with adders on the inputs and outputs to be able to move the pixels around before and after the transformation. This allows for us to do any 2D linear transform, at 5 numbers per second. 2inputs * 16bits * 5bits/sec = 160bits per second of bandwidth.
The idea will be to feed the vertices of a .obj file into this, then send the vertices and edges to the line drawers to connect them, drawing 1 frame every 40 seconds or less.
1920x1080p @ 60FPS #ComputerEngineering #VectorProcessor #ProcessorBIGGEST RENDER EVER - 11 lines in parallel by Penscii, Nano, and TheWildJarviWildEngineering2020-10-13 | Okay so Nano updated topred.fr to 1.16 and using 1.16.3 clients with lithium, phosphor, and sodium, we can run this without client side lag allowing us to record this marvelous achievement.
There are 12 line drawers attached but we only drew 11 lines. The line drawers(designed by Penscii) are 6 ticks in delay per pixel. If we were drawing 12 lines we get 2 pixels per tick.
1920x1080p @ 60FPS #ComputerEngineering #LineDrawing #ASICStar Rendered with 6 lines drawn at once. 1 pixel every tick by Penscii, Nano & TheWildJarviWildEngineering2020-10-11 | This is a star rendered at 1 pixel every redstone tick. The line drawers output a pixel every 6 ticks; 3 line drawers make up one unit which can draw 3 lines at an average of 2 ticks per pixel. this saturated the screen x,y decoder throughput capabilities so another x,y decoder was attached with another 3 line drawers. This is how we achieve 1 pixel every redstone tick.
1920x1080p @ 60FPS #ComputerEngineering #Render #ASICLogical Redstone Tutorial 3: 2 Tick pipelineable X,Y decoder with Passthrough!WildEngineering2020-09-23 | You can speed up the AND gate by removing my mistake of having an extra repeater coming from the decoded Y address to save a tick. You can also move the decoded Y address 1 block closer.
Todays episode is a continuation of last weeks where we improve the matrix decoder so that it is torchless, synced and is able to be stacked so that you can have as many x,y decoders on a single screen that you need.
Coming up next will be making the original 1 dimensional decoders torchless as well, then I will show how to make a matrix decoder for a giant ROM bank. Continuing on Decoder I will start introducing BCD and we will then make a combinational binary to BCD converter. I hope you are all excited for what's coming up in the following uploads! :)
1920x1080p @ 60FPS #ComputerEngineering #Redstone #TutorialLogical Redstone Tutorial 2: Our First Matrix DecoderWildEngineering2020-09-19 | In todays video, we revisit the decoder built in the last tutorial, and improve the design to make a larger decoder. This build is specifically designed for screens, but the concept can be adapted for addressing RAM, ROM or anything you need to address with a decoder.
Matrix decoder just implies the fact that the screen is more than one dimensional.
1920x1080p @ 60FPS #Redstone #Minecraft #Tutorial #DecoderExploring the Mandelbrot set using my custom ASIC.[github in description]WildEngineering2020-08-23 | I have updated my mandelbrot renderer to now zoom and pan using much cleaner logic. You can download it and try it for yourself here: github.com/TheWildJarvi/MandelPlotter-Zoom-and-Pan
1920x1080p @ 60FPS #ComputerEngineering #Mandelbrot #ASICintelliRed Progress UpdateWildEngineering2020-08-16 | I have an update on my 22tick, 6 stage, 16bit, MIPS CPU named intelliRed. If you have any questions please leave a comment below and please also like and subscribe/hit the bell. Happy redstoning.
intelliRed decorative art made by _pseudocode music made by jash jash's sound cloud: soundcloud.com/s5yirr1glkak
#ComputerEngineering #MIPS16 #intelliRedDAY 2: Live Building a 16 bit 6 stage CPU in MinecraftWildEngineering2020-07-20 | Today is the 3rd day of streaming this build! i would like to copy the ISA documentation into Minecraft and I would like to address the RAM and the MMIO so i can prepare to implement those instructions. Please subscribe and hit the bell if you like my contnet and check out the links below!
#ComputerEngineering #Pipeline #CPULogical Redstone Tutorial 1: 3 Decoder Designs in 30 MinutesWildEngineering2020-07-06 | In today's tutorial we will be designing 3 different types of decoders for different use cases! If you enjoy, please leave a like, comment, and join the discord in the link below!
#ComputerEngineering #Decoders #TutorialDAY 2: Live Building a 16 bit 6 stage CPU in MinecraftWildEngineering2020-07-04 | Well I've been working on this fora while and figured I might as well lived stream me working on it some more. I hope you all enjoy, leave a like, comment and subscribe, and check out the discord in the link below.
#ComputerEngineering #Pipeline #CPULive Building a 16 bit 6 stage CPU in MinecraftWildEngineering2020-07-03 | Well I've been working on this fora while and figured I might as well lived stream me working on it some more. I hope you all enjoy, leave a like, comment and subscribe, and check out the discord in the link below.
#ComputerEngineering #Pipeline #CPULogic World Stream Recap: Multiplier and Squarer CircuitsWildEngineering2020-06-17 | So if you didn't want to watch the entire stream this basically shows most of the base hardware that will be used to render mandelbrot in Logic World. The upcoming live streams will continue to focus on achieving this goal!
Hey everyone, Ive decided to make a tutorial series for logical redstone because the last time I did this was more than 5 years ago. This tutorial covers basic logic gates and their NOR and NAND forms respectively.
Please let me know what you think of the video, if it was helpful, if it was too quick, if it required too much base knowledge, etc. I want to improve my content and I need your help!
Hello everyone and thanks for watching, By the time this video releases I will be back and at it, working on the test bed more. This is a test fixture for a fiber optic board set that was designed out of house and I have to verify that the boards will work for their rated speeds. If you have any questions please leave them in the comments below. - Jarvi