tesla500 | DDR3 Interface PCB layout timelapse - Part 2 @tesla500 | Uploaded January 2012 | Updated October 2024, 7 hours ago.
Time lapse of a DDR3 Layout, taken at 1fps. Total time to layout ~38 hours. This is a very long video, check the index at the beginning if you don't want to watch the whole thing.
0:00 DDR1 Address/Command/Clock
2:35 DDR1 data
9:55 DDR1 cleanup
11:55 Bypass capacitor placement, general routing
29:20 Length matching
35:25 Address/Command/Clock termination
Time lapse of a DDR3 Layout, taken at 1fps. Total time to layout ~38 hours. This is a very long video, check the index at the beginning if you don't want to watch the whole thing.
0:00 DDR1 Address/Command/Clock
2:35 DDR1 data
9:55 DDR1 cleanup
11:55 Bypass capacitor placement, general routing
29:20 Length matching
35:25 Address/Command/Clock termination
