tesla500 | DDR3 Interface PCB layout timelapse - Part 1 @tesla500 | Uploaded January 2012 | Updated October 2024, 23 hours ago.
Time lapse of a DDR3 Layout, taken at 1fps. Total time to layout ~38 hours. This is a very long video, check the index at the beginning if you don't want to watch the whole thing.

0:05 Component placement finalization
5:45 Bypass capacitor placement
16:40 DRAM via placement
18:10 DDR0 Address/Command/Clock
25:40 DDR0 data
35:10 DDR0 cleanup