Uploaded August 2026 | Updated September 2026, 1 week ago

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Learn how to configure and run NoC-SE (Network-on-Chip Synthesis Engine) in Arm Interconnect Architect within Arm Socrates. In this training walkthrough, you'll learn how to define traffic and timing requirements, configure floorplanning constraints, and use NoC-SE to automatically generate a Network-on-Chip topology that meets your system design objectives.

This video covers:

Configuring NoC-SE synthesis settings and optimization strategies
Defining traffic-aware and timing-aware synthesis requirements
Creating basic and advanced traffic models to represent realistic workloads
Assigning bandwidth, latency, and traffic profiles between interfaces
Building path scenarios and traffic use cases for system-level analysis
Creating floorplans, die blocks, and power domain boundaries
Defining physical layout constraints and routing regions
Positioning interfaces and memory controller nodes (MCNs)
Running NoC-SE synthesis and reviewing the generated topology
Using design rule checks (DRC) to validate configurations before synthesis

By the end of this walkthrough, you'll understand how NoC-SE translates high-level design requirements into an optimized interconnect topology, helping accelerate NoC design while balancing traffic, timing, and physical implementation constraints.

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