AI Stack: Accelerating AI Infrastructure:The Role of 400G and PCIe 8.0 in Next-Gen Interconnects @SNIAVideo
AI Stack: Accelerating AI Infrastructure:The Role of 400G and PCIe 8.0 in Next-Gen Interconnects  @SNIAVideo
Uploaded January 2026 | Updated September 2026, 2 weeks ago
As AI workloads continue to scale, the physical infrastructure supporting them must evolve to deliver the performance, reliability, and efficiency required by modern data-intensive applications. This webinar will focus on the interconnect foundations of AI infrastructure, including storage. There will be an emphasis on the form factors, connectors, cables, and transceivers standards that enable scalable and interoperable systems.

We’ll explore how SNIA’s SFF Technical Work Group is contributing to the development of physical layer standards that support high-performance interconnects and storage devices used in AI environments. Topics will include the importance of transceiver innovation and the need to evolve; the role that form factors like EDSFF play; and how innovative cabling and connector designs support the adoption of high-speed signaling technologies like PCIe 8.0 and beyond.

This session is ideal for architects, engineers, and technologists who want to understand how physical infrastructure standards are enabling the next generation of AI systems.
Read the webinar Q&A blog: "Q&A: 400G and PCIe 8.0 in Next-Gen Interconnects" snia.org/blog/2026/qa-400g-and-pcie-80-next-gen-interconnects

Key Concepts:
• Transceiver development for out-of-box signaling
• Connectors and cables for high-speed inbox signaling
• Copper vs. optical and the challenges of both
• SSD form factor innovations and their impact on density and thermal design
Presented by Anthony Constantine, Micron Technology; Tom Palkert, Samtec; Erik Smith, Dell Technologies
Learn More:
Read the Q&A blog: snia.org/blog/2026/qa-400g-and-pcie-80-next-gen-interconnects
Listen to the Podcast: youtu.be/qBZ6vtGgdHE
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AI Stack: Accelerating AI Infrastructure:The Role of 400G and PCIe 8.0 in Next-Gen Interconnects

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