Uploaded June 2019 | Updated September 2026, 1 week ago
The control lines to the address registers that determine which register is asserting to the address bus is the last bundle of wires I've not added control circuitry for. In this video I add that to finish of the bus control circuitry. I also wire the bus claim control line from the fetch unit into pipeline stage 2 so it so it plays nicely with the fetch unit.
I add instructions and control for memory reads, these do not fully work as the processor currently lacks the memory bridge that connects the memory data bus to the main bus (This will come in a later video).
The control lines to the address registers that determine which register is asserting to the address bus is the last bundle of wires I've not added control circuitry for. In this video I add that to finish of the bus control circuitry. I also wire the bus claim control line from the fetch unit into pipeline stage 2 so it so it plays nicely with the fetch unit.
I add instructions and control for memory reads, these do not fully work as the processor currently lacks the memory bridge that connects the memory data bus to the main bus (This will come in a later video).
